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PIC16F87/88 Data Sheet
18/20/28-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology
2003 Microchip Technology Inc.
Preliminary
DS30487B
Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable."
*
* *
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, InCircuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified.
DS30487B-page ii
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
18/20/28-Pin Enhanced FLASH MCUs with nanoWatt Technology
Low-Power Features:
* Power Managed modes: - Primary RUN: RC oscillator, 76 A, 1 MHz, 2V - RC_RUN: 7 A, 31.25 kHz, 2V - SEC_RUN: 9 A, 32 kHz, 2V - SLEEP: 0.1 A, 2V * Timer1 Oscillator: 1.8 A, 32 kHz, 2V * Watchdog Timer: 2.2 A, 2V * Two-Speed Oscillator Start-up
Pin Diagram
18-Pin DIP, SOIC
RA2/AN2/CVREF/ VREFRA3/AN3/VREF+/ C1OUT RA4/AN4/T0CKI/ C2OUT RA5/MCLR/VPP VSS RB0/INT/CCP1(1) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1 Note 1:
(1)
1 2 3 4 5 6 7 8 9
18 17 16
RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD RB7/AN6/PGD/ T1OSI RB6/AN5/PGC/ T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL
PIC16F88
15 14 13 12 11 10
Oscillators:
* Three Crystal modes: - LP, XT, HS: up to 20 MHz * Two External RC modes * One External Clock mode: - ECIO: up to 20 MHz * Internal oscillator block: - 8 user selectable frequencies: 31 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
Special Microcontroller Features:
* 100,000 erase/write cycles Enhanced FLASH program memory typical * 1,000,000 typical erase/write cycles EEPROM data memory typical * EEPROM Data Retention: > 40 years * In-Circuit Serial ProgrammingTM (ICSPTM) via two pins * Processor read/write access to program memory * Low-Voltage Programming * In-Circuit Debugging via two pins * Extended Watchdog Timer (WDT): - Programmable period from 1 ms to 268s * Wide operating voltage range: 2.0V to 5.5V
Peripheral Features:
* Capture, Compare, PWM (CCP) module: - Capture is 16-bit, max. resolution is 12.5 ns - Compare is 16-bit, max. resolution is 200 ns - PWM max. resolution is 10-bit * 10-bit, 7-channel Analog-to-Digital Converter * Synchronous Serial Port (SSP) with SPITM (Master/Slave) and I2CTM (Slave) * Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI) with 9-bit address detection: - RS-232 operation using internal oscillator (no external crystal required) * Dual Analog Comparator module: - Programmable on-chip voltage reference - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs are externally accessible
Program Memory Device FLASH # Single Word (bytes) Instructions 7168 7168 4096 4096 Data Memory SRAM (bytes) 368 368 EEPROM (bytes) 256 256 I/O Pins 16 16
10-bit CCP A/D (ch) (PWM) n/a 1 1 1
USART
Comparators
SSP
Timers 8/16-bit 2/1 2/1
PIC16F87 PIC16F88
Y Y
2 2
Y Y
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 1
PIC16F87/88
Pin Diagrams
18-Pin DIP, SOIC
RA2/AN2/CVREF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/VPP VSS RB0/INT/CCP1(1) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(1) 1 2 4 5 6 7 8 9 3 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD RB7/PGD/T1OSI RB6/PGC/T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL
20-Pin SSOP
RA2/AN2/CVREF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/VPP VSS AVSS RB0/INT/CCP1(1) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(1) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD AVDD RB7/PGD/T1OSI RB6/PGC/T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL
18-Pin DIP & SOIC
RA2/AN2/CVREF/VREFRA3/AN3/VREF+/C1OUT RA4/AN4/T0CKI/C2OUT RA5/MCLR/VPP VSS RB0/INT/CCP1(1) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(1) 1 2 4 5 6 7 8 9 3 18 17 16 15 14 13 12 11 10 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL
20-Pin SSOP
RA2/AN2/CVREF/VREFRA3/AN3/VREF+/C1OUT RA4/AN4/T0CKI/C2OUT RA5/MCLR1/VPP VSS AVSS RB0/INT/CCP1(1) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(1) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD AVDD RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI RB5/SS/TX/CK RB4/SCK/SCL
Note 1:
The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
DS30487B-page 2
Preliminary
PIC16F88
PIC16F88
PIC16F87
PIC16F87
2003 Microchip Technology Inc.
PIC16F87/88
Pin Diagrams (Cont'd)
RA4/T0CKI/C2OUT RA3/AN3/C1OUT RA2/AN2/CVREF
28-Pin QFN
RA1/AN1 24
RA0/AN0 23
NC
28
27
26
25
22 21 20 19
RA5/MCLR/VPP NC VSS NC AVSS NC RB0/INT/CCP1(1)
1 2 3 4 5 6 7 10 11 12 13 14 8 9
NC
RA7/OSC1/CLKI RA6/OSC2/CLKO VDD NC AVDD RB7/PGD/T1OSI RB6/PGC/T1OSO/T1CKI
PIC16F87
18 17 16 15
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1(1)
NC
RA4/AN4/T0CKI/C2OUT
RA3/AN3/VREF+/C1OUT
28-Pin QFN
RA2/AN2/CVREF/VREF-
RA1/AN1 24
RA0/AN0 23
NC
RB5/SS/TX/CK
RB4/SCK/SCL
28
27
26
25
22 21 20 19
RA5/MCLR/VPP NC VSS NC AVSS NC RB0/INT/CCP1(1)
1 2 3 4 5 6 7 10 11 12 13 14 8 9
NC
NC
RA7/OSC1/CLKI RA6/OSC2/CLKO VDD NC AVDD RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI
PIC16F88
18 17 16 15
RB1/SDI/SDA
RB2/SDO/RX/DT
RB3/PGM/CCP1(1)
NC
Note 1:
The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
2003 Microchip Technology Inc.
Preliminary
RB5/SS/TX/CK
RB4/SCK/SCL
NC
DS30487B-page 3
PIC16F87/88
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................. 11 3.0 Data EEPROM and FLASH Program Memory ........................................................................................................................... 27 4.0 Oscillator Configurations ............................................................................................................................................................ 35 5.0 I/O Ports ..................................................................................................................................................................................... 51 6.0 Timer0 Module ........................................................................................................................................................................... 67 7.0 Timer1 Module ........................................................................................................................................................................... 71 8.0 Timer2 Module ........................................................................................................................................................................... 79 9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 81 10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 87 11.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART)................................................................ 97 12.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 113 13.0 Comparator Module.................................................................................................................................................................. 121 14.0 Comparator Voltage Reference Module ................................................................................................................................... 127 15.0 Special Features of the CPU .................................................................................................................................................... 129 16.0 Instruction Set Summary .......................................................................................................................................................... 149 17.0 Development Support............................................................................................................................................................... 157 18.0 Electrical Characteristics .......................................................................................................................................................... 163 19.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 191 20.0 Packaging Information.............................................................................................................................................................. 193 Appendix A: Revision History............................................................................................................................................................. 199 Appendix B: Device Differences......................................................................................................................................................... 199 Index .................................................................................................................................................................................................. 201 On-Line Support................................................................................................................................................................................. 209 Systems Information and Upgrade Hot Line ...................................................................................................................................... 209 Reader Response .............................................................................................................................................................................. 210 PIC16F87/88 Product Identification System ...................................................................................................................................... 211
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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DS30487B-page 4
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
1.0 DEVICE OVERVIEW
TABLE 1-1:
This document contains device specific information for the operation of the PIC16F87/88 devices. Additional information may be found in the PICmicro(R) Mid-Range MCU Reference Manual (DS33023) which may be downloaded from the Microchip web site. This Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. The PIC16F87/88 belongs to the Mid-Range family of the PICmicro(R) devices. Block diagrams of the devices are shown in Figure 1-1 and Figure 1-2. These devices contain features that are new to the PIC16 product line: * Low-power modes: RC_RUN allows the core and peripherals to be clocked from the INTRC, while SEC_RUN allows the core and peripherals to be clocked from the low-power Timer1. Refer to Section 4.7 "Power Managed Modes" for further details. * Internal RC oscillator with eight selectable frequencies, including 31.25 kHz, 125 kHz, 250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, and 8 MHz. The INTRC can be configured as a primary or secondary clock source. Refer to Section 4.5 "Internal Oscillator Block" for further details. * The Timer1 module current consumption has been greatly reduced from 20 A (previous PIC16 devices) to 1.8 A typical (32 kHz at 2V), which is ideal for real-time clock applications. Refer to Section 7.0 "Timer1 Module" for further details. * Extended Watchdog Timer (WDT) that can have a programmable period from 1 ms to 268s. The WDT has its own 16-bit prescaler. Refer to Section 15.12 "Watchdog Timer (WDT)" for further details. * Two-Speed Start-up: When the oscillator is configured for LP, XT, or HS, this feature will clock the device from the INTRC while the oscillator is warming up. This, in turn, will enable almost immediate code execution. Refer to Section 15.12.3 "Two-Speed Clock Start-up Mode" for further details. * Fail-Safe Clock Monitor: This feature will allow the device to continue operation if the primary or secondary clock source fails by switching over to the INTRC. * The A/D module has a new register for PIC16 devices named ANSEL. This register allows easier configuration of analog or digital I/O pins.
AVAILABLE MEMORY IN PIC16F87/88 DEVICES
Program FLASH 4K x 14 Data Memory 368 x 8 Data EEPROM 256 x 8
Device PIC16F87/88
There are 16 I/O pins that are user configurable on a pin-to-pin basis. Some pins are multiplexed with other device functions. These functions include: * * * * * * * * * * External Interrupt Change on PORTB Interrupt Timer0 Clock Input Low-power Timer1 Clock/Oscillator Capture/Compare/PWM 10-bit, 7-channel A/D Converter (PIC16F88 only) SPITM/I2CTM Two Analog Comparators USART MCLR (RA5) can be configured as an Input
Table 1-2 details the pinout of the device with descriptions and details for each pin.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 5
PIC16F87/88
FIGURE 1-1: PIC16F87 DEVICE BLOCK DIAGRAM
13 FLASH Program Memory 4K x 14 Program Bus 8 Level Stack (13-bit) Program Counter
Data Bus
8
PORTA RA0/AN0 RA1/AN1 RA2/AN2/CVREF RA3/AN3/C1OUT RA4/T0CKI/C2OUT RA5/MCLR/VPP RA6/OSC2/CLKO RA7/OSC1/CLKI PORTB RB0/INT/CCP1(2) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(2) RB4/SCK/SCL RB5/SS/TX/CK RB6/PGC/T1OSO/T1CKI RB7/PGD/T1OSI
RAM File Registers 368 x 8 RAM Addr(1) 9
14 Instruction reg Direct Addr 7
Addr MUX 8 Indirect Addr
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
W reg
RA5/MCLR
VDD, VSS
Timer2
Timer1
Timer0
SSP
USART
CCP1
Data EE 256 Bytes
Comparators
Note 1: 2:
Higher order bits are from the STATUS register. The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
DS30487B-page 6
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
FIGURE 1-2: PIC16F88 DEVICE BLOCK DIAGRAM
13 FLASH Program Memory 4K x 14 Program Bus 8 Level Stack (13-bit) Program Counter Data Bus 8 PORTA RA0/AN0 RA1/AN1 RA2/AN2/CVREF/VREFRA3/AN3/VREF+/C1OUT RA4/AN4/T0CKI/C2OUT RA5/MCLR/VPP RA6/OSC2/CLKO RA7/OSC1/CLKI PORTB Indirect Addr RB0/INT/CCP1(2) RB1/SDI/SDA RB2/SDO/RX/DT RB3/PGM/CCP1(2) RB4/SCK/SCL RB5/SS/TX/CK RB6/AN5/PGC/T1OSO/T1CKI RB7/AN6/PGD/T1OSI
RAM File Registers 368 x 8 RAM Addr(1) 9
14 Instruction reg Direct Addr 7
Addr MUX 8
FSR reg STATUS reg 8 3
Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
MUX
ALU
W reg
RA5/MCLR
VDD, VSS
Timer2
Timer1
Timer0
10-bit A/D
SSP
USART
CCP1
Data EE 256 Bytes
Comparators
Note 1: 2:
Higher order bits are from the STATUS register. The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 7
PIC16F87/88
TABLE 1-2:
Pin Name
PIC16F87/88 PINOUT DESCRIPTION
PDIP/ SOIC Pin# SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description PORTA is a bidirectional I/O port.
RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/CVREF/VREFRA2 AN2 CVREF VREF-(4) RA3/AN3/VREF+/C1OUT RA3 AN3 VREF+(4) C1OUT RA4/AN4/T0CKI/C2OUT RA4 AN4(4) T0CKI C2OUT RA5/MCLR/VPP RA5 MCLR VPP RA6/OSC2/CLKO RA6 OSC2 CLKO
17
19
23 I/O I TTL Analog TTL Analog TTL Analog Analog TTL Analog Analog Bidirectional I/O pin. Analog input channel 0. Bidirectional I/O pin. Analog input channel 1. Bidirectional I/O pin. Analog input channel 2. Comparator VREF output. A/D reference voltage (Low) input. Bidirectional I/O pin. Analog input channel 3. A/D reference voltage (High) input. Comparator 1 output. Bidirectional I/O pin. Analog input channel 4. Clock input to the TMR0 timer/counter. Comparator 2 output. Input pin. Master Clear (Reset). Input/programming voltage input. This pin is an active low RESET to the device. Programming voltage input. Bidirectional I/O pin. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, this pin outputs CLKO signal which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. Bidirectional I/O pin. Oscillator crystal input. External clock source input.
18
20
24 I/O I
1
1
26 I/O I O I
2
2
27 I/O I I O
3
3
28 I/O I I O ST Analog ST
4
4
1 I I P ST ST - ST - -
15
17
20 I/O O O
RA7/OSC1/CLKI RA7 OSC1 CLKI Legend: Note 1: 2: 3: 4: 5:
16
18
21 I/O I I ST ST/CMOS(3) -
I = Input O = Output I/O = Input/Output P = Power - = Not used TTL = TTL Input ST = Schmitt Trigger Input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. PIC16F88 devices only. The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
DS30487B-page 8
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
TABLE 1-2:
Pin Name
PIC16F87/88 PINOUT DESCRIPTION (CONTINUED)
PDIP/ SOIC Pin# SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description
PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT/CCP1(5) RB0 INT CCP1 RB1/SDI/SDA RB1 SDI SDA RB2/SDO/RX/DT RB2 SDO RX DT RB3/PGM/CCP1(5) RB3 PGM CCP1 RB4/SCK/SCL RB4 SCK SCL RB5/SS/TX/CK RB5 SS TX CK RB6/AN5/PGC/T1OSO/ T1CKI RB6 AN5(4) PGC T1OSO T1CKI RB7/AN6/PGD/T1OSI RB7 AN6(4) PGD T1OSI VSS VDD Legend: Note 1: 2: 3: 4: 5: 6 7 7 I/O I I/O 7 8 8 I/O I I/O 8 9 9 I/O O I I/O 9 10 10 I/O I/O I 10 11 12 I/O I/O I 11 12 13 I/O I O I/O 12 13 15 I/O I I/O O I 13 14 16 I/O I I I 5 14 5, 6 3, 5 P P TTL ST(2) ST - - Bidirectional I/O pin. Interrupt-on-change pin. Analog input channel 6. In-circuit debugger and ICSP programming data pin. Timer1 oscillator input. Ground reference for logic and I/O pins. Positive supply for logic and I/O pins. TTL ST(2) ST ST Bidirectional I/O pin. Interrupt-on-change pin. Analog input channel 5. In-circuit debugger and programming clock pin. Timer1 oscillator output. Timer1 external clock input. TTL TTL Bidirectional I/O pin. Interrupt-on-change pin. Slave select for SPI in Slave mode. USART asynchronous transmit. USART synchronous clock. TTL ST ST Bidirectional I/O pin. Interrupt-on-change pin. Synchronous serial clock input/output for SPI. Synchronous serial clock Input for I2C. TTL ST ST Bidirectional I/O pin. Low-Voltage ICSP programming enable pin. Capture input, Compare output, PWM output. TTL ST Bidirectional I/O pin. SPI Data out. USART asynchronous receive. USART synchronous detect. TTL ST ST Bidirectional I/O pin. SPI Data in. I2C Data. TTL ST(1) ST Bidirectional I/O pin. External interrupt pin. Capture input, Compare output, PWM output.
15, 16 17, 19
I = Input O = Output I/O = Input/Output P = Power - = Not used TTL = TTL Input ST = Schmitt Trigger Input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. PIC16F88 devices only. The CCP1 pin is determined by CCPMX in Configuration Word 1 register.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 9
PIC16F87/88
NOTES:
DS30487B-page 10
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
2.0 MEMORY ORGANIZATION
FIGURE 2-1:
There are two memory blocks in the PIC16F87/88 devices. These are the program memory and the data memory. Each block has its own bus so access to each block can occur during the same oscillator cycle. The data memory can be further broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the "core" are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module. The data memory area also contains the data EEPROM memory. This memory is not directly mapped into the data memory but is indirectly mapped. That is, an indirect address pointer specifies the address of the data EEPROM memory to read/write. The PIC16F87/88 device's 256 bytes of data EEPROM memory have the address range 00h-FFh. More details on the EEPROM memory can be found in Section 3.0 "Data EEPROM and FLASH Program Memory". Additional information on device memory may be found in the PICmicro(R) Mid-Range Reference Manual (DS33023).
PROGRAM MEMORY MAP AND STACK: PIC16F87/88
PC<12:0>
CALL, RETURN RETFIE, RETLW
13
Stack Level 1 Stack Level 2
Stack Level 8 RESET Vector 0000h
Interrupt Vector On-chip Program Memory Page 0
0004h 0005h 07FFh 0800h
Page 1 0FFFh 1000h Wraps to 0000h - 03FFh 1FFFh
2.1
Program Memory Organization
The PIC16F87/88 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. For the PIC16F87/88, the first 4K x 14 (0000h-0FFFh) is physically implemented (see Figure 2-1). Accessing a location above the physically implemented address will cause a wraparound. For example, the same instruction will be accessed at locations 020h, 420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h. The RESET vector is at 0000h and the interrupt vector is at 0004h.
2.2
Data Memory Organization
The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 00 01 10 11 Bank 0 1 2 3
Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM. All implemented banks contain SFRs. Some "high use" SFRs from one bank may be mirrored in another bank for code reduction and quicker access (e.g., the STATUS register is in Banks 0-3). Note: EEPROM data memory description can be found in Section 3.0 "Data EEPROM and FLASH Program Memory" of this data sheet.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 11
PIC16F87/88
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly, or indirectly through the File Select Register (FSR).
FIGURE 2-2:
PIC16F87 REGISTER FILE MAP
File Address File Address Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h Indirect addr.(*) TMR0 PCL STATUS FSR WDTCON PORTB File Address 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h File Address Indirect addr.(*) OPTION PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON1 CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE PR2 SSPADD SSPSTAT
PCLATH INTCON EEDATA EEADR EEDATH EEADRH
PCLATH INTCON EECON1 EECON2 Reserved(1) Reserved(1)
TXSTA SPBRG
General Purpose Register 16 Bytes
General Purpose Register 16 Bytes
CMCON CVRCON
1Eh
1Fh 20h General Purpose Register 80 Bytes accesses 70h-7Fh 7Fh Bank 0 * Note 1: Bank 1
11Fh 120h General Purpose Register 80 Bytes accesses 70h-7Fh 16Fh 170h General Purpose Register 80 Bytes accesses 70h - 7Fh
19Fh 1A0h
General Purpose Register 96 Bytes
EFh F0h
1EFh 1F0h
FFh
17Fh Bank 2 Bank 3
1FFh
Unimplemented data memory locations, read as `0'. Not a physical register. This register is reserved, maintain this register clear.
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PIC16F87/88
FIGURE 2-3: PIC16F88 REGISTER FILE MAP
File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.(*) OPTION PCL STATUS FSR TRISA TRISB 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h File Address Indirect addr.(*) 100h 101h TMR0 102h PCL 103h STATUS 104h FSR WDTCON 105h 106h PORTB 107h 108h 109h 10Ah PCLATH 10Bh INTCON 10Ch EEDATA EEADR 10Dh 10Eh EEDATH 10Fh EEADRH 110h File Address Indirect addr.(*) OPTION PCL STATUS FSR TRISB 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h
PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON1 CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG
PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE PR2 SSPADD SSPSTAT
PCLATH INTCON EECON1 EECON2 Reserved(1) Reserved(1)
TXSTA SPBRG ANSEL CMCON CVRCON ADRESL ADCON1 General Purpose Register 80 Bytes
General Purpose Register 16 Bytes
General Purpose Register 16 Bytes
ADRESH ADCON0
11Fh 120h General Purpose Register 80 Bytes 16Fh 170h accesses 70h-7Fh accesses 70h - 7Fh 17Fh Bank 2 Bank 3 General Purpose Register 80 Bytes
19Fh 1A0h
General Purpose Register 96 Bytes
EFh F0h accesses 70h-7Fh 7Fh FFh Bank 1
1EFh 1F0h
1FFh
Bank 0
* Note 1:
Unimplemented data memory locations, read as `0'. Not a physical register. This register is reserved, maintain this register clear.
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DS30487B-page 13
PIC16F87/88
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.
TABLE 2-1:
Address Bank 0 00h(2) 01h 02h(2) 03h(2) 04h(2) 05h 06h 07h 08h 09h 0Ah(1,2) 0Bh(2) 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh INDF TMR0 PCL STATUS FSR PORTA PORTB -- -- -- PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG -- -- -- ADRESH(4) ADCON0(4) Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page
Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx 0000 xxx0 0000 xxxx xxxx 00xx xxxx -- -- --
26, 135 69 17 135 52 58 -- -- -- 135 19, 69, 77 21, 77 23, 34 77, 83 77, 83 72, 83 80, 85 80, 85 90, 95 89, 95 83, 85 83, 85 81, 83 98, 99 103 105 -- -- -- 120 114, 120
Indirect Data Memory Address Pointer PORTA Data Latch when written; PORTA pins when read (PIC16F87) PORTA Data Latch when written; PORTA pins when read (PIC16F88) PORTB Data Latch when written; PORTB pins when read (PIC16F87) PORTB Data Latch when written; PORTB pins when read (PIC16F88) Unimplemented Unimplemented Unimplemented -- GIE -- OSFIF -- PEIE ADIF CMIF -- TMR0IE RCIF -- Write Buffer for the upper 5 bits of the Program Counter INT0IE TXIF EEIF RBIE SSPIF -- TMR0IF CCP1IF -- INT0IF TMR2IF -- RBIF TMR1IF --
---0 0000 0000 000x -000 0000 00-0 ---xxxx xxxx xxxx xxxx
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- -- WCOL T1RUN TOUTPS3 SSPOV T1CKPS1 TOUTPS2 SSPEN T1CKPS0 TOUTPS1 CKP T1OSCEN TOUTPS0 SSPM3 T1SYNC TMR2ON SSPM2 TMR1CS T2CKPS1 SSPM1 TMR1ON T2CKPS0 SSPM0 Timer2 Module Register Synchronous Serial Port Receive Buffer/Transmit Register Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- SPEN -- RX9 CCP1X SREN CCP1Y CREN CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D
-000 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x 0000 0000 0000 0000 -- -- -- xxxx xxxx
USART Transmit Data Register USART Receive Data Register Unimplemented Unimplemented Unimplemented A/D Result Register High Byte ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE -- ADON
0000 00-0
Legend: Note 1: 2: 3: 4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. RA5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'. PIC16F88 device only.
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TABLE 2-1:
Address Bank 1 80h(2) 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah(1,2) 8Bh(2) 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh PR2 SSPADD SSPSTAT -- -- -- TXSTA SPBRG -- ANSEL
(4) (2) (2) (2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page
Name
INDF OPTION PCL STATUS FSR TRISA TRISB -- -- -- PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE --
Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
0000 0000 1111 1111 0000 0000
26, 135 18, 69 135 17 135 52, 126 58, 85 -- -- -- 135 19, 69, 77 20, 80 22, 34 24 40 38 -- 80, 85 95 88, 95 -- -- -- 97, 99 99, 103 120 120 121, 126, 128 120 52, 115, 120
Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C
0001 1xxx xxxx xxxx 1111 1111 1111 1111 -- -- --
Indirect Data Memory Address Pointer TRISA7 TRISA6 TRISA5(3) PORTA Data Direction Register (TRISA<4:0>) PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE -- OSFIE -- -- -- -- PEIE ADIE CMIE -- IRCF2 -- -- TMR0IE RCIE -- -- IRCF1 TUN5 Write Buffer for the upper 5 bits of the Program Counter INT0IE TXIE EEIE -- IRCF0 TUN4 RBIE SSPIE -- -- OSTS TUN3 TMR0IF CCP1IE -- -- IOFS TUN2 INT0IF TMR2IE -- POR SCS1 TUN1 RBIF TMR1IE -- BOR SCS0 TUN0
---0 0000 0000 000x -000 0000 00-0 ------- --qq -000 0000 --00 0000 -- 1111 1111 0000 0000
Unimplemented Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register SMP CKE D/A P S R/W UA BF Unimplemented Unimplemented Unimplemented CSRC TX9 TXEN SYNC -- BRGH TRMT TX9D Baud Rate Generator Register Unimplemented -- C2OUT CVREN ANS6 C1OUT CVROE ANS5 C2INV CVRR ANS4 C1INV -- ANS3 CIS CVR3 ANS2 CM2 CVR2 ANS1 CM1 CVR1 ANS0 CM0 CVR0
0000 0000 -- -- -- 0000 -010 0000 0000 -- -111 1111 0000 0111
CMCON CVRCON ADRESL(4) ADCON1(4)
000- 0000 126, 128 xxxx xxxx
A/D Result Register Low Byte ADFM ADCS2 VCFG1 VCFG0 -- -- -- --
0000 ----
Legend: Note 1: 2: 3: 4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. RA5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'. PIC16F88 device only.
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PIC16F87/88
TABLE 2-1:
Address Bank 2 100h(2) 101h 102h(2) 103h(2) 104h(2) 105h 106h 107h 108h 109h 10Bh(2) 10Ch 10Dh 10Eh 10Fh Bank 3 180h(2) 181h 182h(2) 183h(2) 184h(2) 185h 186h 187h 188h 189h 18Bh(2) 18Ch 18Dh 18Eh 18Fh INDF OPTION PCL STATUS FSR -- TRISB -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO PD Z DC C 0000 0000 1111 1111 0000 0000 0001 1xxx xxxx xxxx -- 1111 1111 -- -- -- -- TMR0IE -- Write Buffer for the upper 5 bits of the Program Counter INT0IE FREE RBIE WRERR TMR0IF WREN INT0IF WR RBIF RD ---0 0000 0000 000x x--x x000 ---- ---0000 0000 0000 0000 135 18, 69 135 17 135 -- 58, 83 -- -- -- 135 19, 69, 77 28, 34 34 -- -- INDF TMR0 PCL STATUS FSR WDTCON PORTB -- -- -- Addressing this location uses contents of FSR to address data memory (not a physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO WDTPS3 PD WDTPS2 Z WDTPS1 DC WDTPS0 C SWDTEN 0000 0000 xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx ---0 1000 xxxx xxxx -- -- -- -- TMR0IE Write Buffer for the upper 5 bits of the Program Counter INT0IE RBIE TMR0IF INT0IF RBIF ---0 0000 0000 000x xxxx xxxx xxxx xxxx --xx xxxx ---- xxxx -- EEPROM Address Register High Byte 26, 135 69 135 17 135 142 58 -- -- -- 135 19, 69, 77 34 34 34 34 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Details on page
Indirect Data Memory Address Pointer -- -- -- PORTB Data Latch when written; PORTB pins when read Unimplemented Unimplemented Unimplemented -- GIE -- PEIE
10Ah(1,2) PCLATH INTCON EEDATA EEADR EEDATH EEADRH
EEPROM Data Register Low Byte EEPROM Address Register Low Byte -- -- -- -- EEPROM Data Register High Byte --
Indirect Data Memory Address Pointer Unimplemented PORTB Data Direction Register Unimplemented Unimplemented Unimplemented -- GIE EEPGD -- PEIE --
18Ah(1,2) PCLATH INTCON EECON1 EECON2 -- --
EEPROM Control Register2 (not a physical register) Reserved, maintain clear Reserved, maintain clear
Legend: Note 1: 2: 3: 4:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as `0', r = reserved. Shaded locations are unimplemented, read as `0'. The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8>, whose contents are transferred to the upper byte of the program counter. These registers can be addressed from any bank. RA5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'. PIC16F88 device only.
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PIC16F87/88
2.2.2.1 STATUS Register
The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as `000u u1uu' (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STATUS register. For other instructions not affecting any status bits, see Section 16.0 "Instruction Set Summary". Note: The C and DC bits operate as a borrow and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.
REGISTER 2-1:
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 IRP bit 7 R/W-0 RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC R/W-x C bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh) RP<1:0>: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes. TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 2: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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Preliminary
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PIC16F87/88
2.2.2.2 OPTION Register
Note: The OPTION register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0, and the weak pull-ups on PORTB. To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. Although the prescaler can be assigned to either the WDT or Timer0, but not both, a new divide counter is implemented in the WDT circuit to give multiple WDT time-out selection. This allows TMR0 and WDT to each have their own scaler. Refer to Section 15.12 "Watchdog Timer (WDT)" for further details.
REGISTER 2-2:
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7
RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value 000 001 010 011 100 101 110 111 TMR0 Rate WDT Rate 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1:1 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128
bit 6
bit 5
bit 4
bit 3
bit 2-0
Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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2.2.2.3 INTCON Register
Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The INTCON register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 GIE bit 7 R/W-0 PEIE R/W-0 TMR0IE R/W-0 INTE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INTF R/W-x RBIF bit 0
bit 7
GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt INTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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Preliminary
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PIC16F87/88
2.2.2.4 PIE1 Register
This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0 -- bit 7 R/W-0 ADIE(1) R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0
bit 7 bit 6
Unimplemented: Read as `0' ADIE: A/D Converter Interrupt Enable bit(1) 1 = Enabled 0 = Disabled Note 1: This bit is only implemented on the PIC16F88. The bit will read `0' on the PIC16F87.
bit 5
RCIE: USART Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TXIE: USART Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit 1 = Enabled 0 = Disabled CCP1IE: CCP1 Interrupt Enable bit 1 = Enabled 0 = Disabled TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enabled 0 = Disabled TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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2.2.2.5 PIR1 Register
This register contains the individual flag bits for the peripheral interrupts. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-5:
PIR1: PERIPHERAL INTERRUPT STATUS REGISTER 1 (ADDRESS 0Ch)
U-0 -- bit 7 R/W-0 ADIF(1) R-0 RCIF R-0 TXIF R-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0
bit 7 bit 6
Unimplemented: Read as `0' ADIF: A/D Converter Interrupt Flag bit(1) 1 = The A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete Note 1: This bit is only implemented on the PIC16F88. The bit will read `0' on the PIC16F87.
bit 5
RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture mode: 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare mode: 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Interrupt Flag bit 1 = A TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = The TMR1 register overflowed (must be cleared in software) 0 = The TMR1 register did not overflow
bit 4
bit 3
bit 2
bit 1
bit 0
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC16F87/88
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
R/W-0 OSFIE bit 7 R/W-0 CMIE U-0 -- R/W-0 EEIE U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' EEIE: EEPROM Write Operation Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4
bit 3-0
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2.2.2.7 PIR2 Register
The PIR2 register contains the flag bit for the EEPROM write operation interrupt.
.
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
REGISTER 2-7:
PIR2: PERIPHERAL INTERRUPT STATUS REGISTER 2 (ADDRESS 0Dh)
R/W-0 OSFIF bit 7 R/W-0 CMIF U-0 -- R/W-0 EEIF U-0 -- U-0 -- U-0 -- U-0 -- bit 0
bit 7
OSFIF: Oscillator Fail Interrupt Flag bit 1 = System oscillator failed, clock input has changed to INTRC (must be cleared in software) 0 = System clock operating CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed (must be cleared in software) 0 = Comparator input has not changed Unimplemented: Read as `0' EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software) 0 = The write operation is not complete or has not been started Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5 bit 4
bit 3-0
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Preliminary
DS30487B-page 23
PIC16F87/88
2.2.2.8
Note:
PCON Register
Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
Note:
The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), a Brown-out Reset, an external MCLR Reset and WDT Reset.
BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred. The BOR status bit is a `don't care' and is not necessarily predictable if the brownout circuit is disabled (by clearing the BOREN bit in the Configuration Word register).
REGISTER 2-8:
PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 POR R/W-x BOR bit 0
bit 7-2 bit 1
Unimplemented: Read as `0' POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
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PIC16F87/88
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte comes from the PCL register which is a readable and writable register. The upper bits (PC<12:8>) are not readable but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-4 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> PCH). Note 1: There are no status bits to indicate stack overflow or stack underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions, or the vectoring to an interrupt address.
2.4
Program Memory Paging
FIGURE 2-4:
LOADING OF PC IN DIFFERENT SITUATIONS
PCL 8 7 0 Instruction with PCL as Destination ALU
PCH 12 PC 5 PCLATH<4:0>
8
PCLATH PCH 12 PC 2 PCLATH<4:3> 11 11 10 8 7 PCL 0 GOTO,CALL Opcode <10:0>
All PIC16F87/88 devices are capable of addressing a continuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction, the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruction, the user must ensure that the page select bits are programmed so that the desired program memory page is addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits is not required for the RETURN instructions (which POPs the address from the stack). Note: The contents of the PCLATH register are unchanged after a RETURN or RETFIE instruction is executed. The user must rewrite the contents of the PCLATH register for any subsequent subroutine calls or GOTO instructions.
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the application note, "AN556, Implementing a Table Read".
Example 2-1 shows the calling of a subroutine in page 1 of the program memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine (if interrupts are used).
EXAMPLE 2-1:
CALL OF A SUBROUTINE IN PAGE 1 FROM PAGE 0
2.3.2
STACK
ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 CALL SUB1_P1 : : ORG 0x900 SUB1_P1 : : RETURN
The PIC16F87/88 family has an 8-level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on).
;Select page 1 ;(800h-FFFh) ;Call subroutine in ;page 1 (800h-FFFh) ;page 1 (800h-FFFh) ;called subroutine ;page 1 (800h-FFFh) ;return to ;Call subroutine ;in page 0 ;(000h-7FFh)
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Preliminary
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PIC16F87/88
2.5 Indirect Addressing, INDF and FSR Registers
A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.
The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself, indirectly (FSR = 0) will read 00h. Writing to the INDF register indirectly results in a no operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>) as shown in Figure 2-5.
EXAMPLE 2-2:
MOVLW MOVWF CLRF INCF BTFSS GOTO :
INDIRECT ADDRESSING
0x20 FSR INDF FSR,F FSR,4 NEXT ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue
NEXT
CONTINUE
FIGURE 2-5:
DIRECT/INDIRECT ADDRESSING
Direct Addressing Indirect Addressing 0 IRP 7 FSR Register 0
RP1:RP0
6
From Opcode
Bank Select
Location Select 00 00h 01 80h 10 100h 11 180h
Bank Select
Location Select
Data Memory(1)
7Fh Bank 0 Note 1:
FFh Bank 1
17Fh Bank 2
1FFh Bank 3
For register file map detail, see Figure 2-2 or Figure 2-3.
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3.0 DATA EEPROM AND FLASH PROGRAM MEMORY
3.1 EEADR and EEADRH
The EEADRH:EEADR register pair can address up to a maximum of 256 bytes of data EEPROM, or up to a maximum of 8K words of program EEPROM. When selecting a data address value, only the LSByte of the address is written to the EEADR register. When selecting a program address value, the MSByte of the address is written to the EEADRH register and the LSByte is written to the EEADR register. If the device contains less memory than the full address reach of the address register pair, the Most Significant bits of the registers are not implemented. For example, if the device has 128 bytes of data EEPROM, the Most Significant bit of EEADR is not implemented on access to data EEPROM.
The data EEPROM and FLASH program memory are readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers. There are six SFRs used to read and write this memory: * * * * * * EECON1 EECON2 EEDATA EEDATH EEADR EEADRH
When interfacing the data memory block, EEDATA holds the 8-bit data for read/write and EEADR holds the address of the EEPROM location being accessed. The PIC16F87/88 devices have 256 bytes of data EEPROM with an address range from 00h to 0FFh. When writing to unimplemented locations, the charge pump will be turned off. When interfacing the program memory block, the EEDATA and EEDATH registers form a two-byte word that holds the 14-bit data for read/write, and the EEADR and EEADRH registers form a two-byte word that holds the 13-bit address of the EEPROM location being accessed. The PIC16F87/88 devices have 4K words of program FLASH with an address range from 0000h to 0FFFh. Addresses above the range of the respective device will wraparound to the beginning of program memory. The EEPROM data memory allows single byte read and write. The FLASH program memory allows single word reads and four-word block writes. Program memory writes must first start with a 32-word block erase, then write in 4-word blocks. A byte write in data EEPROM memory automatically erases the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device for byte or word operations. When the device is code protected, the CPU may continue to read and write the data EEPROM memory. Depending on the settings of the write protect bits, the device may or may not be able to write certain blocks of the program memory; however, reads of the program memory are allowed. When code protected, the device programmer can no longer access data or program memory; this does NOT inhibit internal reads or writes.
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses. Control bit EEPGD determines if the access will be a program or data memory access. When clear, as it is when reset, any subsequent operations will operate on the data memory. When set, any subsequent operations will operate on the program memory. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set in software. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write or erase operation. On power-up, the WREN bit is clear. The WRERR bit is set when a write (or erase) operation is interrupted by a MCLR, or a WDT Time-out Reset during normal operation. In these situations, following RESET, the user can check the WRERR bit and rewrite the location. The data and address will be unchanged in the EEDATA and EEADR registers. Interrupt flag bit, EEIF in the PIR2 register, is set when write is complete. It must be cleared in software. EECON2 is not a physical register. Reading EECON2 will read all `0's. The EECON2 register is used exclusively in the EEPROM write sequence.
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Preliminary
DS30487B-page 27
PIC16F87/88
REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x EEPGD bit 7 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Unimplemented: Read as `0' FREE: EEPROM Forced Row Erase bit 1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command 0 = Perform write only WRERR: EEPROM Error Flag bit 1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during normal operation) 0 = The write operation completed WREN: EEPROM Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM WR: Write Control bit 1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit can only be set (not cleared) in software. 0 = Write cycle to the EEPROM is complete RD: Read Control bit 1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate an EEPROM read Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' S = Set only `0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- R/W-x FREE R/W-x WRERR R/W-0 WREN R/S-0 WR R/S-0 RD bit 0
bit 6-5 bit 4
bit 3
bit 2
bit 1
bit 0
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3.3 Reading Data EEPROM Memory
The steps to write to EEPROM data memory are: 1. 2. If step 10 is not implemented, check the WR bit to see if a write is in progress. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. Write the 8-bit data value to be programmed in the EEDATA register. Clear the EEPGD bit to point to EEPROM data memory. Set the WREN bit to enable program operations. Disable interrupts (if enabled). Execute the special five instruction sequence: Write 55h to EECON2 in two steps (first to W, then to EECON2). Write AAh to EECON2 in two steps (first to W, then to EECON2). Set the WR bit. Enable interrupts (if using interrupts). Clear the WREN bit to disable program operations. 10. At the completion of the write cycle, the WR bit is cleared and the EEIF interrupt flag bit is set (EEIF must be cleared by firmware). If step 1 is not implemented, then firmware should check for EEIF to be set, or WR to clear, to indicate the end of the program cycle. 8. 9. To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available in the very next cycle in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read or until it is written to by the user (during a write operation). The steps to reading the EEPROM data memory are: 1. Write the address to EEADR. Make sure that the address is not larger than the memory size of the device. Clear the EEPGD bit to point to EEPROM data memory. Set the RD bit to start the read operation. Read the data from the EEDATA register. 5. 6. 7.
3. 4.
2. 3. 4.
EXAMPLE 3-1:
BANKSEL EEADR MOVF ADDR,W MOVWF EEADR
DATA EEPROM READ
Select Bank of EEADR Data Memory Address to read Select Bank of EECON1 Point to Data memory EE Read Select Bank of EEDATA W = EEDATA
; ; ; ; BANKSEL EECON1 ; BCF EECON1,EEPGD ; BSF EECON1,RD ; BANKSEL EEDATA ; MOVF EEDATA,W ;
3.4
Writing to Data EEPROM Memory
EXAMPLE 3-2:
BANKSEL EECON1
DATA EEPROM WRITE
To write an EEPROM data location, the user must first write the address to the EEADR register and the data to the EEDATA register. Then, the user must follow a specific write sequence to initiate the write for each byte. The write will not initiate if the write sequence is not exactly followed (write 55h to EECON2, write AAh to EECON2, then set WR bit) for each byte. We strongly recommend that interrupts be disabled during this code segment (see Example 3-2). Additionally, the WREN bit in EECON1 must be set to enable write. This mechanism prevents accidental writes to data EEPROM due to errant (unexpected) code execution (i.e., lost programs). The user should keep the WREN bit clear at all times except when updating EEPROM. The WREN bit is not cleared by hardware After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit. EEIF must be cleared by software.
Required Sequence
; Select Bank of ; EECON1 BTFSC EECON1,WR ; Wait for write GOTO $-1 ; to complete BANKSEL EEADR ; Select Bank of ; EEADR MOVF ADDR,W ; MOVWF EEADR ; Data Memory ; Address to write MOVF VALUE,W ; MOVWF EEDATA ; Data Memory Value ; to write BANKSEL EECON1 ; Select Bank of ; EECON1 BCF EECON1,EEPGD; Point to DATA ; memory BSF EECON1,WREN ; Enable writes BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF ; ; ; ; ; ; ; INTCON,GIE ; EECON1,WREN ; INTCON,GIE 55h EECON2 AAh EECON2 EECON1,WR Disable INTs. Write 55h Write AAh Set WR bit to begin write Enable INTs. Disable writes
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Preliminary
DS30487B-page 29
PIC16F87/88
3.5 Reading FLASH Program Memory 3.6 Erasing FLASH Program Memory
To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the "BSF EECON1,RD" instruction to be ignored. The data is available in the very next cycle in the EEDATA and EEDATH registers; therefore, it can be read as two bytes in the following instructions. EEDATA and EEDATH registers will hold this value until another read or until it is written to by the user (during a write operation). The minimum erase block is 32 words. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the FLASH array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 32 words of program memory is erased. The Most Significant 11 bits of the EEADRH:EEADR point to the block being erased. EEADR< 4:0> are ignored. The EECON1 register commands the erase operation. The EEPGD bit must be set to point to the FLASH program memory. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. After the "BSF EECON1,WR" instruction, the processor requires two cycles to setup the erase operation. The user must place two NOP instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms, only during the cycle in which the erase takes place. This is not SLEEP mode, as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the EECON1 write instruction.
EXAMPLE 3-3:
BANKSEL EEADRH MOVF ADDRH, W MOVWF EEADRH
FLASH PROGRAM READ
Select Bank of EEADRH MS Byte of Program Address to read LS Byte of Program Address to read Select Bank of EECON1 Point to PROGRAM memory EE Read Any instructions here are ignored as program memory is read in second cycle after BSF EECON1,RD Select Bank of EEDATA DATAL = EEDATA DATAH = EEDATH
; ; ; ; MOVF ADDRL, W ; MOVWF EEADR ; ; BANKSEL EECON1 ; BSF EECON1, EEPGD ; ; BSF EECON1, RD ; ; NOP ; ; NOP ; ; ; BANKSEL EEDATA ; MOVF EEDATA, W ; MOVWF DATAL ; MOVF EEDATH, W ; MOVWF DATAH ;
3.6.1
FLASH PROGRAM MEMORY ERASE SEQUENCE
The sequence of events for erasing a block of internal program memory location is: 1. 2. Load EEADRH:EEADR with address of row being erased. Set EEPGD bit to point to program memory, set WREN bit to enable writes, and set FREE bit to enable the erase. Disable interrupts. Write 55h to EECON2. Write AAh to EECON2. Set the WR bit. This will begin the row erase cycle. The CPU will stall for duration of the erase.
3. 4. 5. 6. 7.
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PIC16F87/88
EXAMPLE 3-4:
BANKSEL MOVF MOVWF MOVF MOVWF ERASE_ROW BANKSEL BSF BSF BSF ; BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF EECON1, WREN INTCON, GIE INTCON, GIE 55h EECON2 AAh EECON2 EECON1, WR ; ; ; ; ; ; ; ; ; ; ; ; Disable interrupts (if using) Write 55h Write AAh Start Erase (CPU stall) Any instructions here are ignored as processor halts to begin Erase sequence processor will stop here and wait for Erase complete after Erase processor continues with 3rd instruction Disable writes Enable interrupts (if using) EECON1 EECON1, EEPGD EECON1, WREN EECON1, FREE ; ; ; ; Select Bank of EECON1 Point to PROGRAM memory Enable Write to memory Enable Row Erase operation
ERASING A FLASH PROGRAM MEMORY ROW
EEADRH ADDRH, W EEADRH ADDRL, W EEADR ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase
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Preliminary
DS30487B-page 31
PIC16F87/88
3.7 Writing to FLASH Program Memory
There are 4 buffer register words and all four locations MUST be written to with correct data. After the "BSF EECON1,WR" instruction, if EEADR xxxxxx11, then a short write will occur. This short write only transfers the data to the buffer register. The WR bit will be cleared in hardware after 1 cycle. The core will not halt and there will be no EEWHLT signal generated. After the "BSF EECON1,WR" instruction, if EEADR = xxxxxx11, then a long write will occur. This will simultaneously transfer the data from EEDATH:EEDATA to the buffer registers and begin the write of all four words. The processor will execute the next instruction and then ignore the subsequent instruction. The user should place NOP instructions into the second words. The processor will then halt internal operations for typically 2 msec in which the write takes place. This is not SLEEP mode, as the clocks and peripherals will continue to run. After the write cycle, the processor will resume operation with the 3rd instruction after the EECON1 write instruction. After each long write, the 4 buffer registers will be reset to 3FFF.
FLASH program memory may only be written to if the destination address is in a segment of memory that is not write protected, as defined in bits WRT1:WRT0 of the device configuration word (Register 15-1). FLASH program memory must be written in four-word blocks. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where EEADR<1:0> = 00. At the same time, all block writes to program memory are done as write only operations. The program memory must first be erased. The write operation is edge-aligned, and cannot occur across boundaries. To write to the program memory, the data must first be loaded into the buffer registers. There are four 14-bit buffer registers and they are addressed by the low 2 bits of EEADR. Loading data into the buffer registers is accomplished via the EEADR, EEADT, EECON1 and EECON2 registers as follows: * * * * * Set EECON1 PGD and WREN Write address to EEADRH:EEADR Write data to EEDATA:EEDATH Write 55, AA to EECON2 Set WR bit in EECON1
FIGURE 3-1:
BLOCK WRITES TO FLASH PROGRAM MEMORY
7 5 EEDATH 07 EEDATA 0
6
First word of block to be written
8
All buffers are transferred to FLASH automatically after this word is written
14
EEADR<1:0> = 00 Buffer Register EEADR<1:0> = 01
14
EEADR<1:0> = 10
14
EEADR<1:0> = 11
14
Buffer Register
Buffer Register
Buffer Register
Program Memory
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An example of the complete four-word write sequence is shown in Example 3-5. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed.
EXAMPLE 3-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following: ; ; ; ; ; ; 1. 2. 3. 4. 5. 6. The 32 words in the erase block have already been erased. A valid starting address (the least significant bits = '00') is loaded into EEADRH:EEADR This example is starting at 0x100, this is an application dependent setting. The 8 bytes (4 words) of data are loaded, starting at an address in RAM called ARRAY. This is an example only, location of data to program is application dependent. word_block is located in data memory. BANKSEL EECON1 BSF EECON1,EEPGD BSF EECON1,WREN BANKSEL word_block MOVLW .4 MOVWF word_block BANKSEL MOVLW MOVWF MOVLW MOVWF BANKSEL MOVLW MOVWF LOOP BANKSEL MOVF MOVWF INCF MOVF MOVWF INCF BANKSEL MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BANKSEL INCF BANKSEL DECFSZ GOTO EEDATA INDF,W EEDATA FSR,F INDF,W EEDATH FSR,F EECON1 0x55 EECON2 0xAA EECON2 EECON1,WR ;indirectly load EEDATA ;increment data pointer ;indirectly load EEDATH ;increment data pointer EEADRH 0x01 EEADRH 0x00 EEADR ARRAY ARRAY FSR ;prepare for WRITE procedure ;point to program memory ;allow write cycles
;prepare for 4 words to be written ;Start writing at 0x100 ;load HIGH address ;load LOW address ;initialize FSR to start of data
;required sequence
Required Sequence
;set WR bit to begin write ;instructions here are ignored as processor
EEADR EEADR,f word_block word_block,f loop
;load next word address ;have 4 words been written? ;NO, continue with writing
BANKSEL EECON1 BCF EECON1,WREN BSF INTCON,GIE
;YES, 4 words complete, disable writes ;enable interrupts
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Preliminary
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3.8 Protection Against Spurious Write 3.9 Operation During Code Protect
There are conditions when the device should not write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. When the data EEPROM is code protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled. External write access to the program memory is also disabled. When program memory is code protected, the microcontroller can read and write to program memory normally, as well as execute instructions. Writes by the device may be selectively inhibited to regions of the memory depending on the setting of bits WRT1:WRT0 of the configuration word (see Section 15.1 "Configuration Bits" for additional information). External access to the memory is also disabled.
TABLE 3-1:
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND FLASH PROGRAM MEMORIES
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other RESETS
Address 10Ch 10Dh 10Eh 10Fh 18Ch 18Dh 0Dh 8Dh Legend:
Name
EEDATA EEPROM/FLASH Data Register Low Byte EEADR EEDATH EEADRH EEPROM/FLASH Address Register Low Byte -- -- -- -- -- CMIF CMIE EEPROM/FLASH Data Register High Byte -- -- -- -- -- FREE EEIF EEIE -- WRERR -- -- EEPROM/FLASH Address Register High Byte WREN -- -- WR -- -- RD -- --
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu ---- -xxx ---- -uuu x--x x000 x--x q000 ---- ---- ---- ---00-0 ---- 00-0 ---00-0 ---- 00-0 ----
EECON1 EEPGD PIR2 PIE2 OSFIF OSFIE
EECON2 EEPROM Control Register 2 (not a physical register)
x = unknown, u = unchanged, - = unimplemented, read as `0', q = value depends upon condition. Shaded cells are not used by data EEPROM or FLASH program memory.
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4.0
4.1
OSCILLATOR CONFIGURATIONS
Oscillator Types
TABLE 4-1:
CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR (FOR DESIGN GUIDANCE ONLY)
Crystal Freq 32 kHz 200 kHz 1 MHz 4 MHz Typical Capacitor Values Tested: C1 C2 33 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF
The PIC16F87/88 can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight modes (modes 5-8 are new PIC16 oscillator configurations): 1. 2. 3. 4. 5. 6. 7. 8. LP XT HS RC RCIO INTIO1 INTIO2 ECIO Low-Power Crystal Crystal/Resonator High-Speed Crystal/Resonator External Resistor/Capacitor with FOSC/4 output on RA6 External Resistor/Capacitor with I/O on RA6 Internal Oscillator with FOSC/4 output on RA6 and I/O on RA7 Internal Oscillator with I/O on RA6 and RA7 External Clock with I/O on RA6
Osc Type
LP XT
33 pF 56 pF 15 pF 15 pF 15 pF 15 pF 15 pF
HS
4 MHz 8 MHz 20 MHz
Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Note 1: Higher capacitance increases the stability of oscillator but also increases the start-up time. 2: Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 3: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application.
4.2
Crystal Oscillator/Ceramic Resonators
In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (see Figure 4-1 and Figure 4-2). The PIC16F87/88 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications.
FIGURE 4-1:
CRYSTAL OPERATION (HS, XT, OR LP OSC CONFIGURATION)
OSC1
PIC16F87/88
C1(1) XTAL OSC2 C2(1) RS(2) To Internal Logic RF(3) SLEEP
Note1: See Table 4-1 for typical values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen (typically between 2 M to 10 M).
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Preliminary
DS30487B-page 35
PIC16F87/88
FIGURE 4-2: CERAMIC RESONATOR OPERATION (HS OR XT OSC CONFIGURATION)
OSC1 C1
(1)
4.3
External Clock Input
PIC16F87/88
The ECIO Oscillator mode requires an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from SLEEP mode. In the ECIO Oscillator mode, the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 4-3 shows the pin connections for the ECIO Oscillator mode.
RES OSC2 C2(1) RS(2)
RF(3)
SLEEP
To Internal Logic
FIGURE 4-3:
Note 1: See Table 4-2 for typical values of C1 and C2. 2: A series resistor (RS) may be required. 3: RF varies with the resonator chosen (typically between 2 M to 10 M). Clock from Ext. System RA6
EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION)
OSC1/CLKI PIC16F87/88 I/O (OSC2)
TABLE 4-2:
CERAMIC RESONATORS (FOR DESIGN GUIDANCE ONLY)
Typical Capacitor Values Used: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz OSC1 56 pF 47 pF 33 pF 27 pF 22 pF OSC2 56 pF 47 pF 33 pF 27 pF 22 pF
HS
Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values were not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Note: When using resonators with frequencies above 3.5 MHz, the use of HS mode, rather than XT mode, is recommended. HS mode may be used at any VDD for which the controller is rated. If HS is selected, it is possible that the gain of the oscillator will overdrive the resonator. Therefore, a series resistor should be placed between the OSC2 pin and the resonator. As a good starting point, the recommended value of RS is 330.
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PIC16F87/88
4.4 RC Oscillator 4.5 Internal Oscillator Block
For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 4-4 shows how the R/C combination is connected. In the RC Oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. The PIC16F87/88 devices include an internal oscillator block, which generates two different clock signals; either can be used as the system's clock source. This can eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source, which can be used to directly drive the system clock. It also drives the INTOSC postscaler which can provide a range of six clock frequencies from 125 kHz to 4 MHz. The other clock source is the internal RC oscillator (INTRC) which provides a 31.25 kHz (32 s nominal period) output. The INTRC oscillator is enabled by selecting the INTRC as the system clock source, or when any of the following are enabled: * * * * Power-up Timer Watchdog Timer Two-Speed Start-up Fail-Safe Clock Monitor
FIGURE 4-4:
VDD REXT
RC OSCILLATOR MODE
OSC1 CEXT VSS
Internal Clock
These features are discussed in greater detail in Section 15.0 "Special Features of the CPU". The clock source frequency (INTOSC direct, INTRC direct, or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 40). Note: Throughout this data sheet, when referring specifically to a generic clock source, the term "INTRC" may also be used to refer to the clock modes using the internal oscillator block. This is regardless of whether the actual frequency used is INTOSC (8 MHz), the INTOSC postscaler, or INTRC (31.25 kHz).
PIC16F87/88
OSC2/CLKO FOSC/4 Recommended values: 3 k REXT 100 k CEXT > 20 pF
The RCIO Oscillator mode (Figure 4-5) functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).
FIGURE 4-5:
VDD REXT
RCIO OSCILLATOR MODE
OSC1 CEXT VSS RA6 I/O (OSC2)
Internal Clock
PIC16F87/88
Recommended values: 3 k REXT 100 k CEXT > 20 pF
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Preliminary
DS30487B-page 37
PIC16F87/88
4.5.1 INTRC MODES 4.5.2 OSCTUNE REGISTER
Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, after which it can be used for digital I/O. Two distinct configurations are available: * In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. * In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output. The internal oscillator's output has been calibrated at the factory but can be adjusted in the application. This is done by writing to the OSCTUNE register (Register 4-1). The tuning sensitivity is constant throughout the tuning range. The OSCTUNE register has a tuning range of 12.5%. When the OSCTUNE register is modified, the INTOSC and INTRC frequencies will begin shifting to the new frequency. The INTRC clock will reach the new frequency within 8 clock cycles (approximately 8 * 32 s = 256 s); the INTOSC clock will stabilize within 1 ms. Code execution continues during this shift. There is no indication that the shift has occurred. Operation of features that depend on the 31.25 kHz INTRC clock source frequency, such as the WDT, Fail-Safe Clock Monitor and peripherals, will also be affected by the change in frequency.
REGISTER 4-1:
OSCTUNE: OSCILLATOR TUNING REGISTER (ADDRESS 90h)
U-0 -- bit 7 U-0 -- R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0
bit 7-6 bit 5-0
Unimplemented: Read as `0' TUN<5:0>: Frequency Tuning bits 011111 = Maximum frequency 011110 = * * * 000001 = 000000 = Center frequency. Oscillator module is running at the calibrated frequency. 111111 = * * * 100000 = Minimum frequency
Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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PIC16F87/88
4.6 Clock Sources and Oscillator Switching
FOSC2:FOSC0 configuration bits in Configuration Register 1. When the bits are set in any other manner, the system clock source is provided by the Timer1 oscillator (SCS1:SCS0 = 01), or from the internal oscillator block (SCS1:SCS0 = 10). After a RESET, SCS<1:0> are always set to `00'. Note: The instruction to immediately follow the modification of SCS<1:0> will have an instruction time (TCY) based on the previous clock source. This should be taken into consideration when developing time dependant code.
The PIC16F87/88 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. PIC16F87/88 devices offer three alternate clock sources. When enabled, these give additional options for switching to the various Power Managed Operating modes. Essentially, there are three clock sources for these devices: * Primary oscillators * Secondary oscillators * Internal oscillator block (INTRC) The primary oscillators include the external Crystal and Resonator modes, the external RC modes, the external Clock mode and the internal oscillator block. The particular mode is defined on POR by the contents of Configuration Word 1. The details of these modes are covered earlier in this chapter. The secondary oscillators are those external sources not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a Power Managed mode. PIC16F87/88 devices offer the Timer1 oscillator as a secondary oscillator. This oscillator continues to run when a SLEEP instruction is executed, and is often the time base for functions such as a real-time clock. Most often, a 32.768 kHz watch crystal is connected between the RB6/T1OSO and RB7/T1OSI pins. Like the LP mode oscillator circuit, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in greater detail in Section 7.6 "Timer1 Oscillator". In addition to being a primary clock source, the internal oscillator block is available as a Power Managed mode clock source. The 31.25 kHz INTRC source is also used as the clock source for several special features, such as the WDT, Fail-Safe Clock Monitor, Power-up Timer, and Two-Speed Start-up. The clock sources for the PIC16F87/88 devices are shown in Figure 4-6. See Section 7.0 "Timer1 Module" for further details of the Timer1 oscillator. See Section 15.1 "Configuration Bits" for Configuration register details.
The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source (31.25 kHz), the INTOSC source (8 MHz), or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz). Changing the configuration of these bits has an immediate change on the internal oscillator's output. The OSTS and IOFS bits indicate the status of the primary oscillator and INTOSC source; these bits are set when their respective oscillators are stable. In particular, OSTS indicates that the Oscillator Start-up Timer has timed out.
4.6.2
CLOCK SWITCHING
Clock switching will occur for the following reasons: * The FCMEN (CONFIG2<0>) bit is set, the device is running from the primary oscillator, and the primary oscillator fails. The clock source will be 31.25 kHz INTRC. * The FCMEN bit is set, the device is running from the T1OSC and T1OSC fails. The clock source will be 31.25 kHz INTRC. * Following a wake-up due to a RESET or a POR, when the device is configured for Two-Speed Start-up mode, switching will occur between the INTRC and the system clock defined by the FOSC<2:0> bits. * A wake-up from SLEEP occurs due to interrupt or WDT wake-up and Two-Speed Start-up is enabled. If the primary clock is XT, HS, or LP, the clock will switch between the INTRC and the primary system clock after 1024 clocks (OST) and 8 clocks of the primary oscillator. This is conditional upon the SCS bits being set equal to `00'. * SCS bits are modified from their original value. * IRCF bits are modified from their original value. Note: Because the SCS bits are cleared on any RESET, no clock switching will occur on a RESET unless the Two-Speed Start-up is enabled and the primary clock is XT, HS, or LP. The device will wait for the primary clock to become stable before execution begins (Two-Speed Start-up disabled).
4.6.1
OSCCON REGISTER
The OSCCON register (Register 4-2) controls several aspects of the system clock's operation, both in full power operation and in Power Managed modes. The System Clock Select bits, SCS1:SCS0, select the clock source that is used when the device is operating in Power Managed modes. When the bits are cleared (SCS<1:0> = 00), the system clock source comes from the main oscillator that is selected by the
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Preliminary
DS30487B-page 39
PIC16F87/88
4.6.3 CLOCK TRANSITION AND WDT
When clock switching is performed, the Watchdog Timer is disabled because the Watchdog ripple counter is used as the Oscillator Start-up Timer. Note: The OST is only used when switching to XT, HS, and LP Oscillator modes. Once the clock transition is complete (i.e., new oscillator selection switch has occurred), the Watchdog counter is re-enabled with the Counter Reset. This allows the user to synchronize the Watchdog Timer to the start of execution at the new clock frequency.
REGISTER 4-2:
OSCCON: OSCILLATOR CONTROL REGISTER (ADDRESS 8Fh)
U-0 -- bit 7 R/W-0 IRCF2 R/W-0 IRCF1 R/W-0 IRCF0 R-0 OSTS(1) R/W-0 IOFS R/W-0 SCS1 R/W-0 SCS0 bit 0
bit 7 bit 6-4
Unimplemented: Read as `0' IRCF<2:0>: Internal RC Oscillator Frequency Select bits 000 = 31.25 kHz 001 = 125 kHz 010 = 250 kHz 011 = 500 kHz 100 = 1 MHz 101 = 2 MHz 110 = 4 MHz 111 = 8 MHz OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Device is running from the primary system clock 0 = Device is running from T1OSC or INTRC as a secondary system clock Note 1: Bit resets to `0' with Two-Speed Start-up mode, and LP, XT, or HS selected as the oscillator mode.
bit 3
bit 2
IOFS: INTOSC Frequency Stable bit 1 = Frequency is stable 0 = Frequency is not stable SCS<1:0>: Oscillator Mode Select bits 00 = Oscillator mode defined by FOSC<2:0> 01 = T1OSC is used for system clock 10 = Internal RC is used for system clock 11 = Reserved Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 1-0
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Preliminary
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PIC16F87/88
FIGURE 4-6: PIC16F87/88 CLOCK DIAGRAM
Primary Oscillator OSC2 SLEEP OSC1 Secondary Oscillator T1OSO T1OSCEN Enable Oscillator To Timer1 OSCCON<6:4> 8 MHz 4 MHz Internal Oscillator Block 8 MHz (INTOSC) 2 MHz Postscaler 101 100 500 kHz 250 kHz 125 kHz 31.25 kHz 011 010 001 000 WDT, FSCM MUX 1 MHz 111 110 Internal Oscillator CPU LP, XT, HS, RC, EC MUX T1OSC Peripherals Config1(FOSC2:FOSC0) SCS<1:0>(T1OSC)
T1OSI
31.25 kHz Source
31.25 kHz (INTRC)
4.6.4
MODIFYING THE IRCF BITS
4.6.5
CLOCK TRANSITION SEQUENCE
The IRCF bits can be modified at any time, regardless of which clock source is currently being used as the system clock. The internal oscillator allows users to change the frequency during run time. This is achieved by modifying the IRCF bits in the OSCCON register. The sequence of events that occur after the IRCF bits are modified is dependent upon the initial value of the IRCF bits before they are modified. If the INTRC (31.25 kHz, IRCF<2:0> = 000) is running and the IRCF bits are modified to any other value than `000', a 4 ms clock switch delay is turned on. Code execution continues at a higher than expected frequency while the new frequency stabilizes. Time sensitive code should wait for the IOFS bit in the OSCCON register to become set before continuing. This bit can be monitored to ensure that the frequency is stable before using the system clock in time critical applications. If the IRCF bits are modified while the internal oscillator is running at any other frequency than INTRC (31.25 kHz IRCF<2:0> 000), there is no need for a 4 ms clock switch delay. The new INTOSC frequency will be stable immediately after the eight falling edges. The IOFS bit will remain set after clock switching occurs. Note: Caution must be taken when modifying the IRCF bits using BCF or BSF instructions. It is possible to modify the IRCF bits to a frequency that may be out of the VDD specification range; for example, VDD = 2.0V and IRCF = 111 (8 MHz).
Following are three different sequences for switching the internal RC oscillator frequency. * Clock before switch: 31.25 kHz (IRCF<2:0> = 000) 1. IRCF bits are modified to an INTOSC/INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. The IOFS bit is clear to indicate that the clock is unstable and a 4 ms delay is started. Time dependent code should wait for IOFS to become set. 5. Switchover is complete. * Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> 000) 1. IRCF bits are modified to INTRC (IRCF<2:0> = 000). 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. Oscillator switchover is complete.
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DS30487B-page 41
PIC16F87/88
* Clock before switch: One of INTOSC/INTOSC postscaler (IRCF<2:0> 000) 1. IRCF bits are modified to a different INTOSC/ INTOSC postscaler frequency. 2. The clock switching circuitry waits for a falling edge of the current clock, at which point CLKO is held low. 3. The clock switching circuitry then waits for eight falling edges of requested clock, after which it switches CLKO to this new clock source. 4. The IOFS bit is set. 5. Oscillator switchover is complete.
4.6.6
OSCILLATOR DELAY UPON POWER-UP, WAKE-UP AND CLOCK SWITCHING
Table 4-3 shows the different delays invoked for various clock switching sequences. It also shows the delays invoked for POR and wake-up.
TABLE 4-3:
OSCILLATOR DELAY EXAMPLES
Frequency 31.25 kHz 32.768 kHz 125 kHz - 8 MHz Following a wake-up from SLEEP mode or 5 s - 10 s (approx.) POR, CPU start-up is invoked to allow the (1) CPU Start-up CPU to become ready for code execution. Oscillator Delay Comments INTRC T1OSC INTOSC/ INTOSC Postscaler EC, RC EC, RC
Switch From Switch To
SLEEP/POR
INTRC/SLEEP INTRC (31.25 kHz) SLEEP INTRC (31.25 kHz) Note 1:
DC - 20 MHz DC - 20 MHz
LP, XT, HS 32.768 kHz - 20 MHz INTOSC/ INTOSC Postscaler 125 kHz - 8 MHz
1024 Clock Cycles (OST) 4 ms
Following a change from INTRC, an OST of 1024 cycles must occur. Refer to Section 4.6.4 "Modifying the IRCF bits" for further details.
The 5 s-10 s start-up delay is based on a 1 MHz system clock.
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PIC16F87/88
4.7
4.7.1
Power Managed Modes
RC_RUN MODE
When SCS bits are configured to run from the INTRC, a clock transition is generated if the system clock is not already using the INTRC. The event will clear the OSTS bit, switch the system clock from the primary system clock (if SCS<1:0> = 00) determined by the value contained in the configuration bits, or from the T1OSC (if SCS<1:0> = 01) to the INTRC clock option, and shut down the primary system clock to conserve power. Clock switching will not occur if the primary system clock is already configured as INTRC.
If the system clock does not come from the INTRC (31.25 kHz) when the SCS bits are changed, and the IRCF bits in the OSCCON register are configured for a frequency other than INTRC, the frequency may not be stable immediately. The IOFS bit (OSCCON<2>) will be set when the INTOSC or postscaler frequency is stable, after approximately 4 ms. After a clock switch has been executed, the OSTS bit is cleared, indicating a low-power mode, and the device does not run from the primary system clock. The internal Q clocks are held in the Q1 state until eight falling edge clocks are counted on the INTRC oscillator. After the eight clock periods have transpired, the clock input to the Q clocks is released and operation resumes (see Figure 4-7).
FIGURE 4-7:
TIMING DIAGRAM FOR XT, HS, LP, EC AND EXTRC TO RC_RUN MODE
TINP(1) TSCS(3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 INTOSC OSC1 System Clock TOSC(2)
TDLY(4) SCS<1:0> Program Counter Note 1: 2: 3: 4: TINP = TOSC = TSCS = TDLY = PC 32 s typical. 50 ns minimum. 8 TINP. 1 TINP. PC + 1 PC + 2 PC + 3
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Preliminary
DS30487B-page 43
PIC16F87/88
4.7.2 SEC_RUN MODE
The core and peripherals can be configured to be clocked by T1OSC using a 32.768 kHz crystal. The crystal must be connected to the T1OSO and T1OSI pins. This is the same configuration as the low-power timer circuit (see Section 7.6 "Timer1 Oscillator"). When SCS bits are configured to run from T1OSC, a clock transition is generated. It will clear the OSTS bit, switch the system clock from either the primary system clock, or INTRC, depending on the value of SCS<1:0> and FOSC<2:0>, to the external low-power Timer1 oscillator input (T1OSC), and shut down the primary system clock to conserve power. After a clock switch has been executed, the internal Q clocks are held in the Q1 state until eight falling edge clocks are counted on the T1OSC. After the eight clock periods have transpired, the clock input to the Q clocks is released and operation resumes (see Figure 4-8). In addition, T1RUN (In T1CON) is set to indicate that T1OSC is being used as the system clock. Note 1: The T1OSCEN bit must be enabled and it is the user's responsibility to ensure T1OSC is stable before clock switching to the T1OSC input clock can occur. 2: When T1OSCEN = 0, the following possible effects result. Original Modified Final SCS<1:0> SCS<1:0> SCS<1:0> 00 01 00 - no change 00 11 10 - INTRC 10 11 10 - no change 10 01 00 - OSC defined by FOSC<2:0> A clock switching event will occur if the final state of the SCS bits is different from the original.
FIGURE 4-8:
TIMING DIAGRAM FOR SWITCHING TO SEC_RUN MODE
TT1P(1) TSCS(3) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 System Clock TOSC(2)
TDLY(4) SCS<1:0> Program Counter PC PC +1 PC + 2 PC +3
Note 1: 2: 3: 4:
TT1P = 30.52 s. TOSC = 50 ns minimum. TSCS = 8 TT1P TDLY = 1 TT1P.
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2003 Microchip Technology Inc.
PIC16F87/88
4.7.3 SEC_RUN/RC_RUN TO PRIMARY CLOCK SOURCE 4.7.3.1 Returning to Primary Clock Source Sequence
When switching from a SEC_RUN or RC_RUN mode back to the primary system clock, following a change of SCS<1:0> to `00', the sequence of events that take place will depend upon the value of the FOSC bits in the Configuration register. If the primary clock source is configured as a crystal (HS, XT, or LP), then the transition will take place after 1024 clock cycles. This is necessary because the crystal oscillator had been powered down until the time of the transition. In order to provide the system with a reliable clock when the changeover has occurred, the clock will not be released to the changeover circuit until the 1024 count has expired. During the oscillator start-up time, the system clock comes from the current system clock. Instruction execution and/or peripheral operation continues using the currently selected oscillator as the CPU clock source, until the necessary clock count has expired to ensure that the primary system clock is stable. To know when the OST has expired, the OSTS bit should be monitored. OSTS = 1 indicates that the Oscillator Start-up Timer has timed out and the system clock comes from the primary clock source. Following the oscillator start-up time, the internal Q clocks are held in the Q1 state until eight falling edge clocks are counted from the primary system clock. The clock input to the Q clocks is then released, and operation resumes with primary system clock determined by the FOSC bits (see Figure 4-10). When in SEC_RUN mode, the act of clearing the T1OSCEN bit in the T1CON register will cause SCS<0> to be cleared, which causes the SCS<1:0> bits to revert to `00' or `10', depending on what SCS<1> is. Although the T1OSCEN bit was cleared, T1OSC will be enabled and instruction execution will continue until the OST time-out for the main system clock is complete. At that time, the system clock will switch from the T1OSC to the primary clock or the INTRC. Following this, the T1 oscillator will be shut down. Note: If the primary system clock is either RC or EC, an internal delay timer (5-10 s) will suspend operation after exiting Secondary Clock mode to allow the CPU to become ready for code execution. Changing back to the primary oscillator from SEC_RUN or RC_RUN can be accomplished by either changing SCS<1:0> to `00', or clearing the T1OSCEN bit in the T1CON register (if T1OSC was the secondary clock). The sequence of events that follows is the same for both modes: 1. If the primary system clock is configured as EC, RC, or INTRC, then the OST time-out is skipped. Skip to step 3. If the primary system clock is configured as an external oscillator (HS, XT, LP), then the OST will be active, waiting for 1024 clocks of the primary system clock. On the following Q1, the device holds the system clock in Q1. The device stays in Q1 while eight falling edges of the primary system clock are counted. Once the eight counts transpire, the device begins to run from the primary oscillator. If the secondary clock was INTRC and the primary is not INTRC, the INTRC will be shut down to save current, providing that the INTRC is not being used for any other function, such as WDT, or Fail-Safe Clock monitoring. If the secondary clock was T1OSC, the T1OSC will continue to run if T1OSCEN is still set, otherwise the T1 oscillator will be shut down.
2.
3. 4. 5. 6.
7.
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PIC16F87/88
FIGURE 4-9: TIMING FOR TRANSITION BETWEEN SEC_RUN/RC_RUN AND PRIMARY CLOCK
Q4 Sec. Osc OSC1 TOST OSC2 Primary Clock System Clock TOSC(3) TSCS(4) Q1 Q2 Q3 Q4 TT1P(1) or TINP(2) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SCS<1:0> OSTS Program Counter PC
TDLY(5)
PC + 1
PC + 2
PC +3
Note 1: 2: 3: 4: 5:
TT1P = 30.52 s. TINP = 32 s typical. TOSC = 50 ns minimum. TSCS = 8 TINP OR 8 TT1P. TDLY = 1 TINP OR 1 TT1P.
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PIC16F87/88
4.7.3.2 Returning to Primary Oscillator with a RESET
A RESET will clear SCS<1:0> back to `00'. The sequence for starting the primary oscillator following a RESET is the same for all forms of RESET, including POR. There is no transition sequence from the alternate system clock to the primary system clock on a RESET condition. Instead, the device will reset the state of the OSCCON register and default to the primary system clock. The sequence of events that take place after this will depend upon the value of the FOSC bits in the Configuration register. If the external oscillator is configured as a crystal (HS, XT, or LP), the CPU will be held in the Q1 state until 1024 clock cycles have transpired on the primary clock. This is necessary because the crystal oscillator had been powered down until the time of the transition. During the oscillator start-up time, instruction execution and/or peripheral operation is suspended. Note: If Two-Speed Clock Start-up mode is enabled, the INTRC will act as the system clock until the OST timer has timed out. 4. there is no oscillator start-up time required because the primary clock is already stable; however, there is a delay between the wake-up event and the following Q2. An internal delay timer of 5-10 s will suspend operation after the RESET to allow the CPU to become ready for code execution. The CPU and peripheral clock will be held in the first Q1. The sequence of events is as follows: 1. 2. A device RESET is asserted from one of many sources (WDT, BOR, MCLR, etc.). The device resets and the CPU start-up timer is enabled if in SLEEP mode. The device is held in RESET until the CPU start-up time-out is complete. If the primary system clock is configured as an external oscillator (HS, XT, LP), then the OST will be active waiting for 1024 clocks of the primary system clock. While waiting for the OST, the device will be held in RESET. The OST and CPU start-up timers run in parallel. After both the CPU start-up and OST timers have timed out, the device will wait for one additional clock cycle and instruction execution will begin.
3.
If the primary system clock is either RC, EC, or INTRC, the CPU will begin operating on the first Q1 cycle following the wake-up event. This means that
FIGURE 4-10:
Q4 T1OSI OSC1
PRIMARY SYSTEM CLOCK AFTER RESET (HS, XT, LP)
Q1 TT1P(1) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST OSC2 TCPU(3) CPU Start-up System Clock Peripheral Clock RESET SLEEP OSTS Program Counter PC 0000h 0001h 0003h 0004h 0005h TOSC(2)
Note 1: TT1P = 30.52 s. 2: TOSC = 50 ns minimum. 3: TCPU = 5-10 s (1 MHz system clock).
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PIC16F87/88
FIGURE 4-11: PRIMARY SYSTEM CLOCK AFTER RESET (EC, RC, INTRC)
TT1P(1) Q4 T1OSI OSC1 OSC2 CPU Start-up System Clock TCPU(2) Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
MCLR
OSTS Program Counter PC 0000h 0001h 0002h 0003h 0004h
Note 1: TT1P = 30.52 s. 2: TCPU = 5 - 10 s (1 MHz system clock).
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TABLE 4-4:
Current System Clock LP, XT, HS, T1OSC, EC, RC
CLOCK SWITCHING MODES
SCS bits <1:0> Modified to: 10 (INTRC) FOSC<2:0> = LP, XT or HS Delay 8 Clocks of INTRC OSTS bit 0 IOFS T1RUN bit bit 1(1) 0 New System Clock INTRC or INTOSC or INTOSC Postscaler T1OSC Comments The internal RC oscillator frequency is dependant upon the IRCF bits.
LP, XT, HS, INTRC, EC, RC INTRC T1OSC
01 (T1OSC) FOSC<2:0> = LP, XT or HS 00 FOSC<2:0> = EC or FOSC<2:0> = RC 00 FOSC<2:0> = LP, XT, HS
8 Clocks of T1OSC
0
N/A
1
T1OSCEN bit must be enabled.
8 Clocks of EC or RC 1024 Clocks (OST) + 8 Clocks of LP, XT, HS 1024 Clocks (OST)
1
N/A
0
EC or RC LP, XT, HS During the 1024 clocks, program execution is clocked from the secondary oscillator until the primary oscillator becomes stable. When a RESET occurs, there is no clock transition sequence. Instruction execution and/or peripheral operation is suspended unless Two-Speed Start-up mode is enabled, after which the INTRC will act as the system clock until the OST timer has expired.
INTRC T1OSC
1
N/A
0
LP, XT, HS
00 (Due to RESET) LP, XT, HS
1
N/A
0
LP, XT, HS
Note 1: If the new clock source is INTOSC or INTOSC postscaler, then the IOFS bit will be set 4 ms after the clock change.
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4.7.4 EXITING SLEEP WITH AN INTERRUPT
If SCS<1:0> = 01 or 10: 1. 2. The device is held in SLEEP until the CPU start-up time-out is complete. After the CPU start-up timer has timed out, the device will exit SLEEP and begin instruction execution with the selected oscillator mode. Note: If a user changes SCS<1:0> just before entering SLEEP mode, the system clock used when exiting SLEEP mode could be different than the system clock used when entering SLEEP mode. As an example, if SCS<1:0> = 01 and T1OSC is the system clock, and the following instructions are executed: BCF SLEEP OSCCON,SCS0
Any interrupt, such as WDT or INT0, will cause the part to leave the SLEEP mode. The SCS bits are unaffected by a SLEEP command and are the same before and after entering and leaving SLEEP. The clock source used after an exit from SLEEP is determined by the SCS bits.
4.7.4.1
1. 2.
Sequence of Events
If SCS<1:0> = 00: The device is held in SLEEP until the CPU start-up time-out is complete. If the primary system clock is configured as an external oscillator (HS, XT, LP), then the OST will be active waiting for 1024 clocks of the primary system clock. While waiting for the OST, the device will be held in SLEEP unless Two-Speed Start-up is enabled. The OST and CPU start-up timers run in parallel. Refer to Section 15.12.3 "Two-Speed Clock Start-up Mode" for details on Two-Speed Start-up. After both the CPU start-up and OST timers have timed out, the device will exit SLEEP and begin instruction execution with the primary clock defined by the FOSC bits.
then a clock change event is executed. If the primary oscillator is XT, LP, or HS, the core will continue to run off T1OSC and execute the SLEEP command. When SLEEP is exited, the part will resume operation with the primary oscillator after the OST has expired.
3.
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5.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro(R) Mid-Range Reference Manual (DS33023). Pin RA4 is multiplexed with the Timer0 module clock input and with analog input to become the RA4/AN4/ T0CKI/C2OUT pin. The RA4/AN4/T0CKI/C2OUT pin is a Schmitt Trigger input and full CMOS output driver. Pin RA5 is multiplexed with the Master Clear module input. The RA5/MCLR/VPP pin is a Schmitt Trigger input. Pin RA6 is multiplexed with the oscillator module input and external oscillator output. Pin RA7 is multiplexed with the oscillator module input and external oscillator input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI are Schmitt Trigger inputs and full CMOS output drivers. Pins RA<1:0> are multiplexed with analog inputs. Pins RA<3:2> are multiplexed with analog inputs, comparator outputs, and VREF inputs. Pins RA<3:0> have TTL inputs and full CMOS output drivers.
5.1
PORTA and the TRISA Register
PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Note: On a Power-on Reset, the pins PORTA<4:0> are configured as analog inputs and read as `0'.
EXAMPLE 5-1:
BANKSEL PORTA CLRF PORTA
INITIALIZING PORTA
; ; ; ; ; ; ; ; ; ; ; select bank of PORTA Initialize PORTA by clearing output data latches Select Bank of ANSEL Configure all pins as digital inputs Value used to initialize data direction Set RA<7:0> as inputs
Reading the PORTA register, reads the status of the pins, whereas writing to it, will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified, and then written to the port data latch.
BANKSEL ANSEL MOVLW 0x00 MOVWF ANSEL MOVLW 0xFF
MOVWF
TRISA
TABLE 5-1:
RA0/AN0 RA1/AN1
PORTA FUNCTIONS
Name Bit# bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 Buffer TTL TTL TTL TTL ST ST ST Function Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF- or comparator VREF output. Input/output or analog input or VREF+ or comparator output. Input/output, analog input or TMR0 external input or comparator output. Input, Master Clear (Reset) or programming voltage input. Input/output, connects to crystal or resonator, oscillator output or 1/4 the frequency of OSC1, and denotes the instruction cycle in RC mode.
RA2/AN2/CVREF/VREF-(2) RA3/AN3/VREF+(2)/C1OUT RA4/AN4(2) /T0CKI/C2OUT
RA5/MCLR/VPP RA6/OSC2/CLKO
RA7/OSC1/CLKI
bit 7
ST/CMOS(1) Input/output, connects to crystal or resonator or oscillator input.
Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise. 2: PIC16F88 only.
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TABLE 5-2:
Address 05h 85h 9Fh 9Bh Legend: Note 1: 2: 3: 4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Bit 7 RA7 Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR xxxx 0000(1) xxx0 0000(2) 1111 1111 -- ANS0 0000 ----111 1111 Value on all other RESETS uuuu 0000(1) uuu0 0000(2) 1111 1111 0000 ----111 1111
Name PORTA TRISA ADCON1 ANSEL
(4)
TRISA7 TRISA6 TRISA5(3) PORTA Data Direction Register ADFM -- ADCS2 ANS6 VCFG1 ANS5 VCFG0 ANS4 -- ANS3 -- ANS2 -- ANS1
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by PORTA. This value applies only to the PIC16F87. This value applies only to the PIC16F88. Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'. PIC16F88 device only.
FIGURE 5-1:
Data Bus
BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS
D CK
Q VDD VDD P
WR PORTA
Q
Data Latch D WR TRISA CK Q N Q VSS Analog Input Mode TTL Input Buffer Q EN RD PORTA D I/O pin
TRIS Latch
RD TRISA
To Comparator To A/D Module Channel Input (PIC16F88 only)
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FIGURE 5-2:
Data Bus WR PORTA D CK
BLOCK DIAGRAM OF RA3/AN3/VREF+/C1OUT PIN
Comparator Mode = 110 Q Comparator 1 Output Q VDD VDD P
Data Latch D WR TRISA CK Q N Q Analog Input Mode VSS VSS RA3 pin
TRIS Latch
TTL Input Buffer RD TRISA Q EN RD PORTA To Comparator To A/D Module Channel Input (PIC16F88 only) To A/D Module Channel VREF+ Input (PIC16F88 only) D
FIGURE 5-3:
Data Bus WR PORTA D CK
BLOCK DIAGRAM OF RA2/AN2/CVREF/VREF- PIN
Q VDD Q VDD P
Data Latch D WR TRISA CK Q N Q VSS Analog Input Mode RA2 pin
TRIS Latch
RD TRISA Q EN RD PORTA To Comparator To A/D Module VREF- (PIC16F88 only) To A/D Module Channel Input (PIC16F88 only) CVROE CVREF D
TTL Input Buffer
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FIGURE 5-4:
Data Bus WR PORTA D CK
BLOCK DIAGRAM OF RA4/AN4/T0CKI/C2OUT PIN
Comparator Mode = 011, 101, 110 Q Comparator 2 Output 1 Q 0 VDD P VDD
Data Latch D WR TRISA CK Q
N Q Analog Input Mode VSS
RA4 pin
TRIS Latch
RD TRISA Q EN RD PORTA TMR0 Clock Input To A/D Module Channel Input (PIC16F88 only) D
Schmitt Trigger Input Buffer
FIGURE 5-5:
BLOCK DIAGRAM OF RA5/MCLR/VPP PIN
MCLRE
MCLR Circuit MCLR Filter
Schmitt Trigger Buffer
Data Bus RD TRIS VSS Q EN RD Port MCLRE D Schmitt Trigger Input Buffer VSS RA5/MCLR/VPP pin
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FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN
From OSC1 CLKO (FOSC/4) VDD P RA6/OSC2/CLKO pin (FOSC = 1x1) Data Bus WR PORTA N VSS Oscillator Circuit VDD
D CK
Q Q
VSS
VDD P
Data Latch D WR TRISA CK Q N Q (FOSC = 1x0, 011) VSS TRIS Latch
RD TRISA Q EN RD PORTA D
Schmitt Trigger Input Buffer
(FOSC = 1x0, 011)
Note 1: I/O pins have protection diodes to VDD and VSS. 2: CLKO signal is 1/4 of the FOSC frequency.
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FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN
From OSC2 Oscillator Circuit VDD (FOSC = 011) Data Bus WR PORTA D CK D WR TRISA CK Q Q RA7/OSC1/CLKI pin(1) VSS
VDD P
Data Latch Q N Q FOSC = 10x VSS Schmitt Trigger Input Buffer Q EN RD PORTA D TRIS Latch
RD TRISA
FOSC = 10x
Note 1: I/O pins have protection diodes to VDD and VSS.
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5.2 PORTB and the TRISB Register
PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'd together to generate the RB port change interrupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTB. This will end the mismatch condition. Clear flag bit RBIF. A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. RB0/INT is an external interrupt input pin and is configured using the INTEDG bit (OPTION<6>). PORTB is multiplexed with several peripheral functions (see Table 5-3). PORTB pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTB pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISB as destination should be avoided. The user should refer to the corresponding peripheral section for the correct TRIS bit settings.
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TABLE 5-3:
Name RB0/INT/CCP1
PORTB FUNCTIONS
Bit# bit 0 Buffer Function TTL/ST(1) Input/output pin or external interrupt input. Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. TTL/ST(5) Input/output pin, SPI data input pin or I2C data I/O pin. Internal software programmable weak pull-up. TTL/ST(4) Input/output pin, SPI data output pin. USART asynchronous receive or synchronous data. Internal software programmable weak pull-up. TTL/ST(2) Input/output pin, programming in LVP mode or Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up. TTL/ST(5) Input/output pin or SPI and I2C clock pin (with interrupt-on-change). Internal software programmable weak pull-up. TTL Input/output pin or SPI slave select pin (with interrupt-on-change). USART asynchronous transmit or synchronous clock. Internal software programmable weak pull-up.
RB1/SDI/SDA RB2/SDO/RX/DT
bit 1 bit 2
RB3/PGM/CCP1(3) RB4/SCK/SCL RB5/SS/TX/CK
bit 3 bit 4 bit 5
RB6/AN5/PGC/T1OSO/ T1CKI RB7/AN6/PGD/T1OSI
bit 6
TTL/ST(2) Input/output pin, analog input(6), serial programming clock (with interrupt-on-change), Timer1 oscillator output pin or Timer1 clock input pin. Internal software programmable weak pull-up. TTL/ST(2) Input/output pin, analog input(6), serial programming data (with interrupt-on-change) or Timer1 oscillator input pin. Internal software programmable weak pull-up.
bit 7
Legend: Note 1: 2: 3:
4: 5: 6:
TTL = TTL input, ST = Schmitt Trigger input This buffer is a Schmitt Trigger input when configured as the external interrupt. This buffer is a Schmitt Trigger input when used in Serial Programming mode. Low-Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP must be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin mid-range devices. This buffer is a Schmitt Trigger input when configured for CCP or SSP mode. This buffer is a Schmitt Trigger input when configured for SPI or I2C mode. PIC16F88 only.
TABLE 5-4:
Address 06h, 106h 86h, 186h 81h, 181h 9Bh
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 RB7 RBPU
--
Bit 6 RB6 INTEDG
ANS6
Bit 5 RB5
Bit 4 RB4
Bit 3 Bit 2 Bit 1 Bit 0 RB3 PSA RB2 PS2 RB1 PS1 RB0 PS0
Value on POR, BOR xxxx xxxx 1111 1111 1111 1111 -111 1111
Value on all other RESETS uuuu uuuu 1111 1111 1111 1111 -111 1111
PORTB TRISB OPTION
ANSEL(1)
PORTB Data Direction Register T0CS T0SE
ANS5 ANS4 ANS3 ANS2 ANS1 ANS0
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. Note 1: PIC16F88 device only.
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FIGURE 5-8: BLOCK DIAGRAM OF RB0 PIN
CCP1 = 1000, 1001, 11xx and CCPMX = 1 CCP 0 1 CCP1 = 000
VDD RBPU(2) Data Bus WR PORTB Data Latch D Q I/O pin(1) CK TRIS Latch D Q WR TRISB CK P Weak Pull-up
TTL Input Buffer
RD TRISB Q RD PORTB D EN
To INT0 or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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FIGURE 5-9: BLOCK DIAGRAM OF RB1 PIN
I2CTM Mode PORT/SSPEN Select SDA Output 1 0 RBPU(2) VDD Weak P Pull-up Data Latch D Q CK VDD
Data Bus WR PORTB
P
N
I/O pin(1)
VSS TRIS Latch D Q WR TRISB CK Q
RD TRISB SDA Drive
TTL Input Buffer Q D EN
RD PORTB
SDA(3)
Schmitt Trigger Buffer
RD PORTB
SDI
Note 1: 2: 3:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. The SDA Schmitt conforms to the I2C specification.
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FIGURE 5-10: BLOCK DIAGRAM OF RB2 PIN
SSPEN SDO 1 0
SPEN DT 1 0
SSPEN + SPEN
VDD RBPU(2) Weak P Pull-up Data Latch Data Bus WR PORTB D CK Q
VDD P
N
I/O pin(1)
VSS TRIS Latch D Q WR TRISB CK Q
RD TRISB DT Drive
TTL Input Buffer Q D EN
RD PORTB
Schmitt Trigger Buffer RX/DT
RD PORTB
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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FIGURE 5-11: BLOCK DIAGRAM OF RB3 PIN
CCP1 = 1000, 1001, 11xx and CCPMX = 0
CCP
CCP1 = 0100, 0101, 0110, 0111 and CCPMX = 0 0 1 or LVP = 1
VDD RBPU(2) Data Bus WR PORTB Data Latch D Q CK TRIS Latch D Q WR TRISB CK TTL Input Buffer Weak P Pull-up
I/O pin(1)
RD TRISB
Q RD PORTB
D EN
To PGM or CCP RD PORTB
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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FIGURE 5-12: BLOCK DIAGRAM OF RB4 PIN
PORT/SSPEN SCK/SCL 1 0 RBPU(2) VDD Weak P Pull-up
VDD SCL Drive Data Bus WR PORTB Data Latch D CK TRIS Latch D WR TRISB CK Q VSS Q
P
N
I/O pin(1)
RD TRISB Latch Q RD PORTB Set RBIF
TTL Input Buffer
D EN Q1
From Other RB7:RB4 pins
Q
D RD PORTB EN Q3
SCK SCL(3)
Note 1: 2: 3:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. The SCL Schmitt conforms to the I2CTM specification.
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FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN
RBPU(2) PORT/SSPEN Data Bus WR PORTB Data Latch D CK TRIS Latch D WR TRISB CK TTL Input Buffer Latch Q RD PORTB Set RBIF D EN Q1 Q Q I/O pin(1) VDD Weak P Pull-up
RD TRISB
From Other RB7:RB4 pins
Q
D RD PORTB EN Q3
SS/TX/CK
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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FIGURE 5-14: BLOCK DIAGRAM OF RB6 PIN
Analog Input Mode RBPU(2) VDD Weak P Pull-up Data Latch Data Bus WR PORTB D CK TRIS Latch D WR TRISB CK Analog Input Mode RD TRISB T1OSCEN/ICD/PROG Mode TTL Input Buffer Q Q I/O pin(1)
Latch Q RD PORTB Set RBIF D EN Q1
From other RB7:RB4 pins
Q
D RD PORTB EN Q3
PGC/T1CKI From T1OSCO Output To A/D Module Channel Input (PIC16F88 only)
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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FIGURE 5-15: BLOCK DIAGRAM OF RB7 PIN
PORT/Program Mode/ICD PGD 1 Analog Input Mode RBPU(2) Data Latch D CK TRIS Latch D WR TRISB CK Q 0 1 Q I/O pin(1) 0 VDD Weak P Pull-up
Data Bus WR PORTB
RD TRISB T1OSCEN PGD DRVEN
T1OSCEN Analog Input Mode TTL Input Buffer Latch Q D EN Q1
RD PORTB Set RBIF
From Other RB7:RB4 pins
Q
D RD PORTB EN Q3
PGD To T1OSCI Input To A/D Module Channel Input (PIC16F88 only)
Note 1: 2:
I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
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6.0 TIMER0 MODULE
The Timer0 module timer/counter has the following features: * * * * * * 8-bit timer/counter Readable and writable 8-bit software programmable prescaler Internal or external clock select Interrupt on overflow from FFh to 00h Edge select for external clock increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.3 "Using Timer0 with an External Clock". The prescaler is mutually, exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 6.4 "Prescaler" details the operation of the prescaler.
Additional information on the Timer0 module is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023). Figure 6-1 is a block diagram of the Timer0 module and the prescaler shared with the WDT.
6.2 6.1 Timer0 Operation
Timer0 operation is controlled through the OPTION register (see Register 2-2). Timer mode is selected by clearing bit T0CS (OPTION<5>). In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the
Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit TMR0IF (INTCON<2>). The interrupt can be masked by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
FIGURE 6-1:
CLKO (= FOSC/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus M U X 8 1 0 M U X Sync 2 Cycles TMR0 reg
0 RA4/T0CKI pin 1 T0SE
T0CS
PSA Prescaler
Set Flag bit TMR0IF on Overflow
0 WDT Timer 31.25 kHz 16-bit Prescaler 1 M U X
8-bit Prescaler 8 8 - to - 1 MUX PS2:PS0
WDT Enable bit
PSA 0 MUX 1 PSA
WDT Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
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6.3 Using Timer0 with an External Clock
Note: Although the prescaler can be assigned to either the WDT or Timer0, but not both, a new divide counter is implemented in the WDT circuit to give multiple WDT time-out selections. This allows TMR0 and WDT to each have their own scaler. Refer to Section 15.12 "Watchdog Timer (WDT)" for further details.
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.
The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x....etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable. Note: Writing to TMR0, when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment.
6.4
Prescaler
There is only one prescaler available, which is mutually exclusively shared between the Timer0 module and the Watchdog Timer. A prescaler assignment for the Timer0 module means that the prescaler cannot be used by the Watchdog Timer, and vice versa. This prescaler is not readable or writable (see Figure 6-1).
REGISTER 6-1:
OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 RBPU bit 7 R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 PS2 R/W-1 PS1 R/W-1 PS0 bit 0
bit 7 bit 6 bit 5
RBPU: PORTB Pull-up Enable bit INTEDG: Interrupt Edge Select bit T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKO) T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module PS<2:0>: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 1:2 000 1:1 1:4 001 1:2 1:8 010 1:4 1 : 16 011 1:8 1 : 32 100 1 : 16 1 : 64 101 1 : 32 1 : 128 110 1 : 64 1 : 256 111 1 : 128 Legend: R = Readable bit - n = Value at POR Note: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 4
bit 3
bit 2-0
To avoid an unintended device RESET, the instruction sequence shown in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.
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EXAMPLE 6-1: CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
; ; ; ; Clear WDT and prescaler Select Bank of OPTION Select TMR0, new prescale value and clock source CLRWDT BANKSEL OPTION MOVLW b'xxxx0xxx' MOVWF OPTION
TABLE 6-1:
Address 01h,101h
REGISTERS ASSOCIATED WITH TIMER0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx INTE T0SE RBIE TMR0IF INTF RBIF 0000 000x PSA PS2 PS1 PS0 1111 1111 Value on all other RESETS uuuu uuuu 0000 000u 1111 1111
TMR0
Timer0 Module Register GIE RBPU PEIE INTEDG TMR0IE T0CS
0Bh,8Bh, INTCON 10Bh,18Bh 81h,181h Legend: OPTION
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by Timer0.
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7.0 TIMER1 MODULE
7.1 Timer1 Operation
The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>). The Timer1 oscillator can be used as a secondary clock source in Low-power modes. When the T1RUN bit is set along with SCS<1:0> = 01, the Timer1 oscillator is providing the system clock. If the Fail-Safe Clock Monitor is enabled, and the Timer1 oscillator fails while providing the system clock, polling the T1RUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. Timer1 can also be used to provide Real-Time Clock (RTC) functionality to applications with only a minimal addition of external components and code overhead. Timer1 can operate in one of three modes: * as a Timer * as a Synchronous Counter * as an Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON<0>). Timer1 also has an internal "RESET input". This RESET can be generated by the CCP1 module as the special event trigger (see Section 9.1 "Capture Mode"). Register 7-1 shows the Timer1 Control register. When the Timer1 oscillator is enabled (T1OSCEN is set), the RB6/T1OSO/T1CKI/PGC and RB7/T1OSI/ PGD pins become inputs. That is, the TRISB<7:6> value is ignored and these pins read as `0'. Additional information on timer modules is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
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REGISTER 7-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as `0' T1RUN: Timer1 System Clock Status bit 1 = System clock is derived from Timer1 oscillator 0 = System clock is derived from another source T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain) T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RB6/AN5/PGC/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R-0 T1RUN R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 T1OSCEN T1SYNC TMR1CS TMR1ON
bit 5-4
bit 3
bit 2
bit 1
bit 0
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7.2 Timer1 Operation in Timer Mode 7.4
Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync.
Timer1 Operation in Synchronized Counter Mode
Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RB7/AN6/PGD/T1OSI, when bit T1OSCEN is set, or on pin RB6/AN5/PGC/T1OSO/ T1CKI, when bit T1OSCEN is cleared. If T1SYNC is cleared, then the external clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter. In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut-off. The prescaler, however, will continue to increment.
7.3
Timer1 Counter Operation
Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit. When Timer1 is being incremented via an external source, increments occur on a rising edge. After Timer1 is enabled in Counter mode, the module must first have a falling edge before the counter begins to increment.
FIGURE 7-1:
T1CKI (Default High)
TIMER1 INCREMENTING EDGE
T1CKI (Default Low)
Note: Arrows indicate counter increments.
FIGURE 7-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit TMR1IF on Overflow TMR1H
TMR1 TMR1L
0 1 TMR1ON On/Off T1SYNC
Synchronized Clock Input
T1OSC 1 T1OSO/T1CKI T1OSCEN FOSC/4 Enable Internal Oscillator(1) Clock Prescaler 1, 2, 4, 8 0 2 T1CKPS1:T1CKPS0 TMR1CS Q Clock Synchronize det
T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
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7.5 Timer1 Operation in Asynchronous Counter Mode
7.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE
If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.5.1 "Reading and Writing Timer1 in Asynchronous Counter Mode"). In Asynchronous Counter mode, Timer1 cannot be used as a time base for capture or compare operations.
Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers while the register is incrementing. This may produce an unpredictable value in the timer register. Reading the 16-bit value requires some care. The example codes provided in Example 7-1 and Example 7-2 demonstrate how to write to and read Timer1 while it is running in Asynchronous mode.
EXAMPLE 7-1:
WRITING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled CLRF TMR1L ; Clear Low byte, Ensures no rollover into TMR1H MOVLW HI_BYTE ; Value to load into TMR1H MOVWF TMR1H, F ; Write High byte MOVLW LO_BYTE ; Value to load into TMR1L MOVWF TMR1H, F ; Write Low byte ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
EXAMPLE 7-2:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL MOVF TMR1H, W ; Read high byte SUBWF TMPH, W ; Sub 1st read with 2nd read BTFSC STATUS,Z ; Is result = 0 GOTO CONTINUE ; Good 16-bit read ; TMR1L may have rolled over between the read of the high and low bytes. ; Reading the high and low bytes now will read a good value. MOVF TMR1H, W ; Read high byte MOVWF TMPH MOVF TMR1L, W ; Read low byte MOVWF TMPL ; Re-enable the Interrupt (if required) CONTINUE ; Continue with your code
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7.6 Timer1 Oscillator 7.7
A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low-power oscillator rated up to 32.768 kHz. It will continue to run during all Power Managed modes. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 7-3. Table 7-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper oscillator start-up.
Timer1 Oscillator Layout Considerations
The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 7-3, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator, a grounded guard ring around the oscillator circuit, as shown in Figure 7-4, may be helpful when used on a single-sided PCB, or in addition to a ground plane.
FIGURE 7-3:
EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR
PIC16F87/88
T1OSI
FIGURE 7-4:
C1 33 pF
OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING
VSS
XTAL 32.768 kHz T1OSO C2 33 pF Note: See the Notes with Table 7-1 for additional information about capacitor selection.
OSC1 OSC2
RB7 RB6
TABLE 7-1:
Osc Type LP
CAPACITOR SELECTION FOR THE TIMER1 OSCILLATOR
Freq 32 kHz C1 33 pF C2 33 pF
RB5
7.8
Note 1: Microchip suggests this value as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only.
Resetting Timer1 Using a CCP Trigger Output
If the CCP1 module is configured in Compare mode to generate a "special event trigger" signal (CCP1M3:CCP1M0 = 1011), the signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for Timer1.
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7.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) 7.11 Using Timer1 as a Real-Time Clock
TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.
7.10
Timer1 Prescaler
Adding an external LP oscillator to Timer1 (such as the one described in Section 7.6 "Timer1 Oscillator", above), gives users the option to include RTC functionality to their applications. This is accomplished with an inexpensive watch crystal to provide an accurate time base, and several lines of application code to calculate the time. When operating in SLEEP mode and using a battery or super capacitor as a power source, it can completely eliminate the need for a separate RTC device and battery backup. The application code routine, RTCisr, shown in Example 7-3, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one; additional counters for minutes and hours are incremented as the previous counter overflow. Since the register pair is 16-bits wide, counting up to overflow the register directly from a 32.768 kHz clock would take 2 seconds. To force the overflow at the required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of TMR1H with a BSF instruction. Note that the TMR1L register is never pre-loaded or altered; doing so may introduce cumulative error over many cycles. For this method to be accurate, Timer1 must operate in Asynchronous mode, and the Timer1 overflow interrupt must be enabled (PIE1<0> = 1), as shown in the routine, RTCinit. The Timer1 oscillator must also be enabled and running at all times.
The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
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EXAMPLE 7-3:
RTCinit
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TMR1H 0x80 TMR1H TMR1L b'00001111' T1CON secs mins .12 hours PIE1 PIE1, TMR1IE TMR1H TMR1H,7 PIR1,TMR1IF secs,F secs,w .60 STATUS,Z seconds mins,f mins,w .60 STATUS,Z mins hours,f hours,w .24 STATUS,Z hours ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers
RTCisr
BANKSEL MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BANKSEL BSF RETURN BANKSEL BSF BCF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF INCF MOVF SUBLW BTFSS RETURN CLRF RETURN
; Enable Timer1 interrupt
; Preload for 1 sec overflow ; Clear interrupt flag ; Increment seconds
; ; ; ;
60 seconds elapsed? No, done Clear seconds Increment minutes
; ; ; ;
60 seconds elapsed? No, done Clear minutes Increment hours
; ; ; ;
24 hours elapsed? No, done Clear hours Done
TABLE 7-2:
Address
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
0Bh, 8Bh, INTCON 10Bh, 18Bh 0Ch 8Ch 0Eh 0Fh 10h Legend: PIR1 PIE1 TMR1L TMR1H T1CON
0000 000x 0000 000u
TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register --
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer1 module.
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8.0 TIMER2 MODULE
8.1 Timer2 Prescaler and Postscaler
Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP1 module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF (PIR1<1>)). Timer2 can be shut-off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Register 8-1 shows the Timer2 Control register. Additional information on timer modules is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
Postscaler 1:1 to 1:16 4 EQ Comparator
The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR, WDT Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate a shift clock.
FIGURE 8-1:
Sets Flag bit TMR2IF TMR2 Output(1) RESET
TIMER2 BLOCK DIAGRAM
TMR2 reg
Prescaler 1:1, 1:4, 1:16 2
FOSC/4
PR2 reg
Note 1: TMR2 register output can be software selected by the SSP module as a baud clock.
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REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0 -- bit 7 bit 7 bit 6-3 Unimplemented: Read as `0' TOUTPS<3:0>: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale * * * 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 TOUTPS3 TOUTPS2 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 2
bit 1-0
TABLE 8-1:
Address
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Bit 7 Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF Value on POR, BOR Value on all other RESETS
Name
0Bh, 8Bh, INTCON GIE 10Bh, 18Bh 0Ch 8Ch 11h 12h 92h Legend: PIR1 PIE1 TMR2 T2CON PR2 -- -- --
0000 000x 0000 000u
TMR1IF -000 0000 -000 0000 TMR1IE -000 0000 -000 0000 0000 0000 0000 0000
Timer2 Module Register Timer2 Period Register
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the Timer2 module.
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9.0 CAPTURE/COMPARE/PWM (CCP) MODULE
The CCP module's input/output pin (CCP1) can be configured as RB0 or RB3. This selection is set in bit 12 (CCPMX) of the configuration word. Additional information on the CCP module is available in the PICmicro(R) Mid-Range MCU Reference Manual, (DS33023) and in Application Note AN594, "Using the CCP Modules" (DS00594).
The Capture/Compare/PWM (CCP) module contains a 16-bit register that can operate as a: * 16-bit Capture register * 16-bit Compare register * PWM Master/Slave Duty Cycle register. Table 9-1 shows the timer resources of the CCP module modes. Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match which will reset Timer1 and start an A/D conversion (if the A/D module is enabled).
TABLE 9-1:
CCP MODE - TIMER RESOURCE
Timer Resource Timer1 Timer1 Timer2
CCP Mode Capture Compare PWM
REGISTER 9-1:
CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
U-0 -- bit 7 U-0 -- R/W-0 CCP1X R/W-0 CCP1Y R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0
bit 7-6 bit 5-4
Unimplemented: Read as `0' CCP1X:CCP1Y: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. CCP1M<3:0>: CCP1 Mode Select bits 0000 = Capture/Compare/PWM disabled (resets CCP1 module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCP1IF bit is set) 1001 = Compare mode, clear output on match (CCP1IF bit is set) 1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected); CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3-0
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9.1 Capture Mode
9.1.2 TIMER1 MODE SELECTION
In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on CCP1 pin. An event is defined as: * * * * Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.
9.1.3
SOFTWARE INTERRUPT
An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit, CCP1IF (PIR1<2>), is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.
When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit, CCP1IF, following any such change in operating mode.
9.1.4
CCP PRESCALER
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured as an input by setting the TRISB bit. Note 1: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition. 2: The TRISB bit (0 or 3) is dependent upon the setting of configuration bit 12 (CCPMX).
There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. Example 9-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt.
FIGURE 9-1:
CAPTURE MODE OPERATION BLOCK DIAGRAM
EXAMPLE 9-1:
CLRF MOVLW
CHANGING BETWEEN CAPTURE PRESCALERS
Set Flag bit CCP1IF (PIR1<2>) Prescaler / 1, 4, 16 CCP1 Pin and Edge Detect CCPR1H Capture Enable TMR1H CCP1CON<3:0> Q's TMR1L CCPR1L
MOVWF
CCP1CON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCP1CON ;Load CCP1CON with this ;value
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9.2 Compare Mode
9.2.1 CCP PIN CONFIGURATION
In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 pin is: * Driven high * Driven low * Remains unchanged The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit, CCP1IF, is set. The user must configure the CCP1 pin as an output by clearing the TRISB bit. Note 1: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the data latch. 2: The TRISB bit (0 or 3) is dependent upon the setting of configuration bit 12 (CCPMX).
FIGURE 9-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
Special Event Trigger Set Flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Q S R Output Logic Comparator TMR1H TMR1L
9.2.2
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.
9.2.3
SOFTWARE INTERRUPT MODE
CCP1 pin TRISB Output Enable
Match
When generate software interrupt is chosen, the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled).
9.2.4
SPECIAL EVENT TRIGGER
CCP1CON<3:0> Mode Select
Special event trigger will: * RESET Timer1, but not set interrupt flag bit, TMR1IF (PIR1<0>) * Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D conversion
In this mode, an internal hardware trigger is generated that may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. Note: The special event trigger from the CCP1 module will not set interrupt flag bit TMR1IF (PIR1<0>).
TABLE 9-2:
Address
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Name Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on all other RESETS
0Bh,8Bh INTCON 10BH,18Bh 0Ch 8Ch 86h 0Eh 0Fh 10h 15h 16h 17h PIR1 PIE1 TRISB TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON
0000 000x 0000 000u
CCP1IF TMR2IF
TMR1IF -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000
PORTB Data Direction Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register -- Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- CCP1X CCP1Y
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by Capture and Timer1.
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9.3 PWM Mode
9.3.1 PWM PERIOD
In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTB I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula.
EQUATION 9-1:
PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 8.0 "Timer2 Module") is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output.
Figure 9-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to setup the CCP module for PWM operation, see Section 9.3.3 "Setup for PWM Operation".
FIGURE 9-3:
SIMPLIFIED PWM BLOCK DIAGRAM
CCP1CON<5:4>
Duty Cycle Registers CCPR1L
CCPR1H (Slave) CCP1 pin Comparator (Note 1) S TRISB Clear Timer, CCP1 pin and latch D.C. R Q
9.3.2
PWM DUTY CYCLE
TMR2
Comparator
The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time.
PR2 Note 1:
EQUATION 9-2:
8-bit timer is concatenated with 2-bit internal Q clock or 2 bits of the prescaler to create 10-bit time base.
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register. The CCPR1H register and a 2-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared.
A PWM output (Figure 9-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).
FIGURE 9-4:
Period
PWM OUTPUT
Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2
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The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula.
9.3.3
SETUP FOR PWM OPERATION
EQUATION 9-3:
Resolution
The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISB bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. Note: The TRISB bit (0 or 3) is dependant upon the setting of configuration bit 12 (CCPMX).
=
FOSC log( FPWM log(2)
)
bits
2. 3.
Note:
If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared.
4. 5.
TABLE 9-3:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 0xFF 10 4 0xFF 10 1 0xFF 10 1 0x3F 8 1 0x1F 7 1 0x17 6.6
Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits)
TABLE 9-4:
Address
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF TMR2IF TMR2IE Bit 0 RBIF TMR1IF TMR1IE Value on POR, BOR Value on all other RESETS
Name
0Bh,8Bh INTCON 10Bh,18Bh 0Ch 8Ch
0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000
PIR1 PIE1 TRISB TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON
86h
11h 92h 12h 15h 16h 17h
PORTB Data Direction Register
Timer2 Module Register Timer2 Module Period Register -- Capture/Compare/PWM Register 1 (LSB) Capture/Compare/PWM Register 1 (MSB) -- -- CCP1X CCP1Y
1111 1111 1111 1111
0000 0000 0000 0000 1111 1111 1111 1111
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend:
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by PWM and Timer2.
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NOTES:
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10.0
10.1
SYNCHRONOUS SERIAL PORT (SSP) MODULE
SSP Module Overview
10.2
SPI Mode
and
This section contains register definitions operational characteristics of the SPI module.
The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can operate in one of two modes: * Serial Peripheral Interface (SPI) * Inter-Integrated Circuit (I2C) An overview of I2C operations and additional information on the SSP module can be found in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023). Refer to Application Note AN578, "Use of the SSP Module in the I 2CTM Multi-Master Environment" (DS00578).
SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) * Serial Data In (SDI) * Serial Clock (SCK) RB2/SDO/RX/DT RB1/SDI/SDA RB4/SCK/SCL
Additionally, a fourth pin may be used when in a Slave mode of operation: * Slave Select (SS) RB5/SS/TX/CK When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and the SSPSTAT register (SSPSTAT<7:6>). These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (IDLE state of SCK) Clock Edge (output data on rising/falling edge of SCK) * Clock Rate (Master mode only) * Slave Select mode (Slave mode only) * * * *
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REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0 SMP bit 7 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire(R)) SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode.
R/W-0 CKE
R-0 D/A
R-0 P
(1)
R-0 S
(1)
R-0 R/W
R-0 UA
R-0 BF bit 0
I2C mode:
This bit must be maintained clear.
bit 6
CKE: SPI Clock Edge Select bit SPI mode, CKP = 0: 1 = Data transmitted on rising edge of SCK (Microwire alternate) 0 = Data transmitted on falling edge of SCK SPI mode, CKP = 1: 1 = Data transmitted on falling edge of SCK (Microwire alternate) 0 = Data transmitted on rising edge of SCK I2C mode: This bit must be maintained clear. D/A: Data/Address bit (I2C mode only) In I2 C Slave mode: 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was address P: STOP bit(1) (I2C mode only) 1 = Indicates that a STOP bit has been detected last 0 = STOP bit was not detected last S: START bit(1) (I2C mode only) 1 = Indicates that a START bit has been detected last (this bit is `0' on RESET) 0 = START bit was not detected last R/W: Read/Write Information bit (I2C mode only) Holds the R/W bit information following the last address match, and is only valid from address match to the next START bit, STOP bit, or ACK bit. 1 = Read 0 = Write UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (in I2 C mode only): 1 = Transmit in progress, SSPBUF is full (8 bits) 0 = Transmit complete, SSPBUF is empty Note 1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared). Legend: R = Readable bit - n = Value at POR
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
W = Writable bit `1' = Bit is set
U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 10-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit 1 = An attempt to write the SSPBUF register failed because the SSP module is busy (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow SSPEN: Synchronous Serial Port Enable bit(1) In SPI mode: 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins Note 1: In both modes, when enabled, these pins must be properly configured as input or output. bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Transmit happens on falling edge, receive on rising edge. IDLE state for clock is a high level. 0 = Transmit happens on rising edge, receive on falling edge. IDLE state for clock is a low level. In I2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) SSPM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = OSC/4 0001 = SPI Master mode, clock = OSC/16 0010 = SPI Master mode, clock = OSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1011 = I2C firmware controlled Master mode (Slave IDLE) 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled 1000, 1001, 1010, 1100, 1101 = Reserved Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 SSPOV R/W-0 SSPEN(1) R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0
bit 6
bit 5
bit 3-0
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FIGURE 10-1: SSP BLOCK DIAGRAM (SPI MODE)
Internal Data Bus Read SSPBUF reg Write
To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISB register) appropriately programmed. That is: * SDI must have TRISB<1> set * SDO must have TRISB<2> cleared * SCK (Master mode) must have TRISB<4> cleared * SCK (Slave mode) must have TRISB<4> set * SS must have TRISB<5> set Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE = 1, then the SS pin control must be enabled.
RB1/SDI/SDA SSPSR reg RB2/SDO/RX/DT bit0 Shift Clock
RB5/SS/ TX/CK
SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 4 Edge Select TRISB<4>
TMR2 Output 2 Prescaler TCY 4, 16, 64
RB4/SCK/ SCL
3: When the SPI is in Slave mode with SS pin control enabled (SSPCON<3:0> = 0100), the state of SS pin can affect the state read back from the TRISB<5> bit. The peripheral OE signal from the SSP module into PORTB controls the state that is read back from the TRISB<5> bit. If readmodify-write instructions, such as BSF, are performed on the TRISB register while the SS pin is high, this will cause the TRISB<5> bit to be set, thus disabling the SDO output.
TABLE 10-1:
Address
REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on all other RESETS
0Bh,8Bh INTCON 10Bh,18Bh 0Ch 8Ch 86h 13h 14h 94h Legend: PIR1 PIE1 TRISB SSPBUF SSPCON SSPSTAT
0000 000x 0000 000u
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM1 UA SSPM0 0000 0000 0000 0000 BF 0000 0000 0000 0000
PORTB Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL SSPOV SSPEN SMP CKE D/A CKP P SSPM3 SSPM2 S R/W
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used by the SSP in SPI mode.
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FIGURE 10-2:
SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) SDO SDI (SMP = 0) bit 7 SDI (SMP = 1) bit 7 SSPIF bit 0 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
SPI MODE TIMING, MASTER MODE
FIGURE 10-3:
SS (Optional)
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SCK (CKP = 0) SCK (CKP = 1)
SDO SDI (SMP = 0)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7 SSPIF
bit 0
FIGURE 10-4:
SS
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SCK (CKP = 0) SCK (CKP = 1)
SDO
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDI (SMP = 0) bit 7 SSPIF bit 0
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10.3 SSP I 2C Mode Operation
The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RB4/SCK/SCL pin, which is the clock (SCL), and the RB1/SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISB<4,1> bits. The SSP module functions are enabled by setting SSP Enable bit SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I 2C modes to be selected: * I 2C Slave mode (7-bit address) * I 2C Slave mode (10-bit address) * I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled to support firmware Master mode * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled to support Firmware Master mode * I 2C firmware controlled master operation with START and STOP bit interrupts enabled, Slave is IDLE Selection of any I 2C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISB bits. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. Additional information on SSP I2C operation may be found in the PICmicro(R) Mid-Range MCU Reference Manual (DS33023).
FIGURE 10-5:
SSP BLOCK DIAGRAM (I2C MODE)
Internal Data Bus
Read RB4/SCK/ SCL Shift Clock SSPSR Reg RB1/ SDI/ SDA MSb SSPBUF Reg
Write
10.3.1
LSb Addr Match
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISB<4,1> set). The SSP module will override the input state with the output data, when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and then load the SSPBUF register with the received value currently in the SSPSR register. Either or both of the following conditions will cause the SSP module not to give this ACK pulse: a) b) The buffer full bit, BF (SSPSTAT<0>), was set before the transfer was received. The overflow bit, SSPOV (SSPCON<6>), was set before the transfer was received.
Match Detect
SSPADD Reg START and STOP Bit Detect
Set, RESET S, P Bits (SSPSTAT Reg)
The SSP module has five registers for I2C operation: SSP Control register (SSPCON) SSP Status register (SSPSTAT) Serial Receive/Transmit Buffer register (SSPBUF) SSP Shift register (SSPSR) - Not directly accessible * SSP Address register (SSPADD) * * * *
In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 10-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software did not properly clear the overflow condition. Flag bit, BF, is cleared by reading the SSPBUF register while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the SSP module, are shown in timing parameter #100 and parameter #101.
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10.3.1.1 Addressing 10.3.1.2 Reception
Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit, BF, is set. An ACK pulse is generated. SSP interrupt flag bit, SSPIF (PIR1<3>), is set (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then a no Acknowledge (ACK) pulse is given. An overflow condition is indicated if either bit, BF (SSPSTAT<0>), is set or bit, SSPOV (SSPCON<6>), is set. An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF (PIR1<3>), must be cleared in software. The SSPSTAT register is used to determine the status of the byte.
10.3.1.3
Transmission
In 10-bit Address mode, two address bytes need to be received by the slave device. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit address. Bit R/W (SSPSTAT<2>) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7- 9 for slave transmitter: 1. 2. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of Address, if match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive Repeated START condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.
When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RB4/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RB4/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master device must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master device by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 10-7). An SSP interrupt is generated for each data transfer byte. Flag bit, SSPIF, must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit, SSPIF, is set on the falling edge of the ninth clock pulse. As a slave transmitter, the ACK pulse from the master receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is complete. When the ACK is latched by the slave device, the slave logic is reset (resets SSPSTAT register) and the slave device then monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then, pin RB4/SCK/SCL should be enabled by setting bit CKP.
3. 4. 5.
6. 7. 8. 9.
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TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS
SSPSR SSPBUF Generate ACK Pulse Set bit SSPIF (SSP Interrupt Occurs if Enabled) Yes Yes Yes Yes Status bits as Data Transfer is Received BF 0 1 1 0 Note 1: SSPOV 0 0 1 1 Yes No No No Yes No No No
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
FIGURE 10-6:
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
Receiving Address R/W = 0 ACK Receiving Data Receiving Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P
SDA
A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9
SCL
S
SSPIF (PIR1<3>)
Cleared in software
Bus master terminates transfer
BF (SSPSTAT<0>)
SSPBUF register is read
SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full ACK is not sent
FIGURE 10-7:
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
Receiving Address R/W = 1 A1 ACK D7 D6 D5 D4 Transmitting Data D3 D2 D1 D0 ACK
SDA
A7
A6
A5
A4
A3
A2
SCL
S
1 2 Data is sampled
3
4
5
6
7
8
9
1 SCL held low while CPU responds to SSPIF
2
3
4
5
6
7
8
9
P
SSPIF (PIR1<3>) BF (SSPSTAT<0>) CKP (SSPCON<4>)
Cleared in software
SSPBUF is written in software
From SSP Interrupt Service Routine
Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set)
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10.3.2 MASTER MODE OPERATION 10.3.3 MULTI-MASTER MODE OPERATION
Master mode operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE and both the S and P bits are clear. In Master mode operation, the SCL and SDA lines are manipulated in firmware by clearing the corresponding TRISB<4,1> bit(s). The output level is always low, irrespective of the value(s) in PORTB<4,1>. So, when transmitting data, a `1' data bit must have the TRISB<1> bit set (input) and a `0' data bit must have the TRISB<1> bit cleared (output). The same scenario is true for the SCL line with the TRISB<4> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I2C module. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * START condition * STOP condition * Data transfer byte transmitted/received Master mode operation can be done with either the Slave mode IDLE (SSPM3:SSPM0 = 1011) or with the Slave mode active. When both Master mode operation and Slave modes are used, the software needs to differentiate the source(s) of the interrupt. For more information on Master mode operation, see Application Note AN554, "Software Implementation of I2CTM Bus Master". In Multi-Master mode operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is IDLE and both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs. In Multi-Master mode operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a high level is expected and a low level is present, the device needs to release the SDA and SCL lines (set TRISB<4,1>). There are two stages where this arbitration can be lost: * Address Transfer * Data Transfer When the slave logic is enabled, the slave device continues to receive. If arbitration was lost during the address transfer stage, communication to the device may be in progress. If addressed, an ACK pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time. For more information on Multi-Master mode operation, see Application Note AN578, "Use of the SSP Module in the of I2CTM Multi-Master Environment".
TABLE 10-3:
Address
REGISTERS ASSOCIATED WITH I2C OPERATION
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE
2
Name
Bit 4 INTE TXIF TXIE
Bit 3 RBIE
Bit 2 TMR0IF
Bit 1 INTF
Bit 0 RBIF
Value on POR, BOR 0000 000x -000 0000 -000 0000 xxxx xxxx 0000 0000 0000 0000 0000 0000 1111 1111
Value on all other RESETS 0000 000u -000 0000 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 1111 1111
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 8Ch 13h 93h 14h 94h 86h Legend: Note 1: PIR1 PIE1 SSPBUF SSPADD SSPCON SSPSTAT TRISB
SSPIF CCP1IF TMR2IF TMR1IF SSPIE CCP1IE TMR2IE TMR1IE
Synchronous Serial Port Receive Buffer/Transmit Register Synchronous Serial Port (I C mode) Address Register WCOL SMP(1) SSPOV CKE(1) SSPEN D/A CKP P SSPM3 SSPM2 SSPM1 SSPM0 S R/W UA BF
PORTB Data Direction Register
x = unknown, u = unchanged, - = unimplemented locations read as `0'. Shaded cells are not used by SSP module in SPI mode. Maintain these bits clear in I2C mode.
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NOTES:
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11.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART)
The USART can be configured in the following modes: * Asynchronous (full-duplex) * Synchronous - Master (half-duplex) * Synchronous - Slave (half-duplex) Bit SPEN (RCSTA<7>) and bits TRISB<5,2> have to be set in order to configure pins, RB5/SS/TX/CK and RB2/SDO/RX/DT, as the Universal Synchronous Asynchronous Receiver Transmitter. The USART module also has a multi-processor communication capability, using 9-bit address detection.
The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.) The USART can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.
REGISTER 11-1:
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h)
R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0
bit 7
CSRC: Clock Source Select bit Asynchronous mode: Don't care. Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in Sync mode.
bit 6
bit 5
bit 4
SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as `0' BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High-speed 0 = Low-speed Synchronous mode: Unused in this mode. TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of Transmit Data, can be Parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 3 bit 2
bit 1
bit 0
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REGISTER 11-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h)
R/W-0 SPEN bit 7 bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0
SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RB2/SDO/RX/DT and RB5/SS/TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode: Don't care. Synchronous mode - Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave: Don't care. CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enables interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of Received Data (can be Parity bit, but must be calculated by user firmware) Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
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11.1 USART Baud Rate Generator (BRG)
11.1.1 USART AND INTRC OPERATION
The PIC16F87/88 has an 8 MHz INTRC that can be used as the system clock, thereby eliminating the need for external components to provide the clock source. When the INTRC provides the system clock, the USART module will also use the INTRC as its system clock. Table 11-1 shows some of the INTRC frequencies that can be used to generate the USART's baud rate.
The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free-running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 11-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 11-1. From this, the error in baud rate can be determined. It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.
11.1.2
LOW-POWER MODE OPERATION
The system clock is used to generate the desired baud rate; however, when a low-power mode is entered, the low-power clock source may be operating at a different frequency than in full power execution. In SLEEP mode, no clocks are present. This may require the value in SPBRG to be adjusted.
11.1.3
SAMPLING
The data on the RB2/SDO/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin.
TABLE 11-1:
SYNC 0 1
BAUD RATE FORMULA
BRGH = 0 (Low-speed) (Asynchronous) Baud Rate = FOSC/(64(X + 1)) (Synchronous) Baud Rate = FOSC/(4(X + 1)) BRGH = 1 (High-speed) Baud Rate = FOSC/(16(X + 1)) N/A
Legend: X = value in SPBRG (0 to 255)
TABLE 11-2:
Address 98h 18h 99h Legend:
REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR
Bit 7 CSRC SPEN Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on: POR, BOR 0000 -010 0000 000x 0000 0000 Value on all other RESETS 0000 -010 0000 000x 0000 0000
Name TXSTA RCSTA SPBRG
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used by the BRG.
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TABLE 11-3:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW 0.300 1.202 2.404 8.929 20.833 31.250 -- 62.500 0.244 62.500
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 20 MHz % ERROR -- +1.75 +0.17 +1.73 + 1.72 +8.51 +3.34 +8.51 -- -- FOSC = 4 MHz % ERROR 0 +0.17 +0.17 +6.99 +8.51 +8.51 -- +8.51 -- -- SPBRG value (decimal) 207 51 25 6 2 1 -- 0 255 0 SPBRG value (decimal) -- 255 129 31 15 9 8 4 255 0 FOSC = 16 MHz % ERROR -- +0.17 +0.17 +0.16 +0.16 -3.55 +6.29 +8.51 -- -- SPBRG value (decimal) -- 207 103 25 12 8 6 3 255 0 FOSC = 10 MHz % ERROR -- +0.17 +0.17 +1.73 +1.72 +8.51 -6.99 -9.58 -- -- SPBRG value (decimal) -- 129 64 15 7 4 4 2 255 0
KBAUD -- 1.221 2.404 9.766 19.531 31.250 34.722 62.500 1.221 312.500
KBAUD -- 1.202 2.404 9.615 19.231 27.778 35.714 62.500 0.977 250.000
KBAUD -- 1.202 2.404 9.766 19.531 31.250 31.250 52.083 0.610 156.250
FOSC = 3.6864 MHz % ERROR 0 0 0 0 0 0 -- 0 -- -- SPBRG value (decimal) 191 47 23 5 2 1 -- 0 255 0
KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 -- 57.6 0.225 57.6
TABLE 11-4:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW BAUD RATE (K) KBAUD 0.3 1.2 2.4 9.6 19.2 28.8 33.6 57.6 HIGH LOW -- 1.202 2.404 9.615 19.231 27.798 35.714 62.500 0.977 250.000
BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 20 MHz % ERROR -- -- -- +0.16 +0.16 +0.94 +0.55 +3.34 -- -- FOSC = 4 MHz % ERROR -- +0.17 +0.17 +0.16 +0.16 -3.55 +6.29 +8.51 -- -- SPBRG value (decimal) -- 207 103 25 12 8 6 3 255 0 SPBRG value (decimal) -- -- -- 129 64 42 36 20 255 0 FOSC = 16 MHz % ERROR -- -- -- +0.16 +0.16 +2.13 -0.79 +2.13 -- -- SPBRG value (decimal) -- -- -- 103 51 33 29 16 255 0 FOSC = 10 MHz % ERROR -- -- +1.71 +0.16 +1.72 -1.36 -2.10 -1.36 -- -- SPBRG value (decimal) -- -- 255 64 31 21 18 10 255 0
KBAUD -- -- -- 9.615 19.231 29.070 33.784 59.524 4.883 1250.000
KBAUD -- -- -- 9.615 19.231 29.412 33.333 58.824 3.906 1000.000
KBAUD -- -- 2.441 9.615 19.531 28.409 32.895 56.818 2.441 625.000
FOSC = 3.6864 MHz % ERROR -- 0 0 0 0 0 -2.04 0 -- -- SPBRG value (decimal) -- 191 95 23 11 7 6 3 255 0
KBAUD -- 1.2 2.4 9.6 19.2 28.8 32.9 57.6 0.9 230.4
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TABLE 11-5:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 38.4 57.6
INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)
FOSC = 8 MHz % ERROR -- +0.16 +0.16 +0.16 -6.99 +8.51 +8.51 +8.51 SPBRG value (decimal) -- 103 51 12 6 3 2 1 FOSC = 4 MHz % ERROR 0 +0.16 +0.16 -6.99 +8.51 +8.51 -- 8.51 SPBRG value (decimal) 207 51 25 6 2 1 -- 0 FOSC = 2 MHz % ERROR 0 +0.16 +0.16 +8.51 -- +8.51 -- -- SPBRG value (decimal) 103 25 12 2 -- 0 -- -- FOSC = 1 MHz % ERROR 0 +0.16 -6.99 -- -- -- -- -- SPBRG value (decimal) 51 12 6 -- -- -- -- --
KBAUD NA 1.202 2.404 9.615 17.857 31.250 41.667 62.500
KBAUD 0.300 1.202 2.404 8.929 20.833 31.250 NA 62.500
KBAUD 0.300 1.202 2.404 10.417 NA 31.250 NA NA
KBAUD 0.300 1.202 2.232 NA NA NA NA NA
TABLE 11-6:
BAUD RATE (K) 0.3 1.2 2.4 9.6 19.2 28.8 38.4 57.6
INTRC BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)
FOSC = 8 MHz % ERROR -- -- +0.16 +0.16 +0.16 +2.12 +0.16 -3.55 SPBRG value (decimal) -- -- 207 51 25 16 12 8 FOSC = 4 MHz % ERROR -- +0.16 +0.16 +0.16 +0.16 -3.55 -6.99 +8.51 SPBRG value (decimal) -- 207 103 25 12 8 6 3 FOSC = 2 MHz % ERROR -- +0.16 +0.16 +0.16 -6.99 +8.51 +8.51 +8.51 SPBRG value (decimal) -- 103 51 12 6 3 2 1 FOSC = 1 MHz % ERROR 0 +0.16 +0.16 -6.99 +8.51 +8.51 -- +8.51 SPBRG value (decimal) 207 51 25 6 2 1 -- 0
KBAUD NA NA 2.404 9.615 19.231 29.412 38.462 55.556
KBAUD NA 1.202 2.404 9.615 19.231 27.778 35.714 62.500
KBAUD NA 1.202 2.404 9.615 17.857 31.250 41.667 62.500
KBAUD 0.300 1.202 2.404 8.929 20.833 31.250 NA 62.500
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11.2 USART Asynchronous Mode
In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8 bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on bit BRGH (TXSTA<2>). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver rupt can be enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. TXIF is cleared by loading TXREG. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure 11-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, when transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 11-3). Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the RB5/SS/TX/CK pin will revert to high-impedance. In order to select 9-bit transmission, transmit bit, TX9 (TXSTA<6>), should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register.
11.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in Figure 11-1. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit, TXIF (PIR1<4>), is set. This inter-
FIGURE 11-1:
USART TRANSMIT BLOCK DIAGRAM
Data Bus TXIF TXREG Register 8 MSb (8) *** TSR Register LSb 0 Pin Buffer and Control RB5/SS/TX/CK pin
TXIE
Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN
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When setting up an asynchronous transmission, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 11.1 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. 4. 5. 6. 7. 8. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
2. 3.
FIGURE 11-2:
Write to TXREG BRG Output (Shift Clock) RB5/SS/TX/CK pin
ASYNCHRONOUS MASTER TRANSMISSION
Word 1
START Bit TXIF bit (Transmit Buffer Reg. Empty Flag)
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit
TRMT bit (Transmit Shift Reg. Empty Flag)
Word 1 Transmit Shift Reg
FIGURE 11-3:
Write to TXREG BRG Output (Shift Clock) RB5/SS/TX/CK pin TXIF bit (Interrupt Reg. Flag) TRMT bit (Transmit Shift Reg. Empty Flag)
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)
Word 1 Word 2
START Bit
Bit 0
Bit 1 Word 1
Bit 7/8
STOP Bit START Bit Word 2
Bit 0
Word 1 Transmit Shift Reg.
Word 2 Transmit Shift Reg.
Note:
This timing diagram shows two consecutive transmissions.
TABLE 11-7:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR TMR2IE TRMT Bit 0 R0IF TMR1IF RX9D TMR1IE TX9D Value on: POR, BOR -000 000x -000 0000 0000 -00x 0000 0000 SSPIE CCP1IE -- BRGH -000 0000 0000 -010 0000 0000 Value on all other RESETS -000 000u -000 0000 0000 -00x 0000 0000 -000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA TXREG PIE1 TXSTA
USART Transmit Register
SPBRG Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous transmission.
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11.2.2 USART ASYNCHRONOUS RECEIVER
The receiver block diagram is shown in Figure 11-4. The data is received on the RB2/SDO/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas, the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the Receive (Serial) Shift register (RSR). After sampling the STOP bit, the received data in the RSR is transferred to the RCREG register (if it is empty). If the transfer is complete, flag bit, RCIF (PIR1<5>), is set. The actual interrupt can be enabled/disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the Overrun Error bit, OERR (RCSTA<1>), will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to the RCREG register are inhibited, and no further data will be received. It is, therefore, essential to clear error bit OERR if it is set. Framing Error bit, FERR (RCSTA<2>), is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is essential for the user to read the RCSTA register before reading the RCREG register, in order not to lose the old FERR and RX9D information.
FIGURE 11-4:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN OERR FERR
FOSC
SPBRG Baud Rate Generator
/64 or /16
MSb STOP (8) 7
RSR Register *** 1
LSb 0 START
RB2/SDO/RX/DT Pin Buffer and Control Data Recovery RX9
SPEN
RX9D
RCREG Register
FIFO
Interrupt
RCIF RCIE
8 Data Bus
FIGURE 11-5:
RX pin Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note:
ASYNCHRONOUS RECEPTION
START bit bit 0 bit 1 bit 7/8 STOP bit START bit bit 0 bit 7/8 STOP bit START bit bit 7/8 STOP bit
Word 1 RCREG
Word 2 RCREG
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
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PIC16F87/88
When setting up an asynchronous reception, follow these steps: 1. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 11.1 "USART Baud Rate Generator (BRG)"). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. 7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 8. Read the 8-bit received data by reading the RCREG register. 9. If any error occurred, clear the error by clearing enable bit CREN. 10. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. 6.
2. 3. 4. 5.
TABLE 11-8:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x -000 0000 0000 -00x 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE -- BRGH TRMT TX9D -000 0000 0000 -010 0000 0000 Value on all other RESETS 0000 000u -000 0000 0000 -00x 0000 0000 -000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF FERR OERR RX9D
RCREG USART Receive Register
Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 105
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11.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT
When setting up an asynchronous reception with address detect enabled: * Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH. * Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. * If interrupts are desired, then set enable bit RCIE. * Set bit RX9 to enable 9-bit reception. * Set ADDEN to enable address detect. * Enable the reception by setting enable bit CREN. * Flag bit RCIF will be set when reception is complete, and an interrupt will be generated if enable bit RCIE was set. * Read the RCSTA register to get the ninth bit and determine if any error occurred during reception. * Read the 8-bit received data by reading the RCREG register, to determine if the device is being addressed. * If any error occurred, clear the error by clearing enable bit CREN. * If the device has been addressed, clear the ADDEN bit to allow data bytes and address bytes to be read into the receive buffer, and interrupt the CPU.
FIGURE 11-6:
USART RECEIVE BLOCK DIAGRAM
x64 Baud Rate CLK CREN OERR FERR
FOSC
SPBRG
/ 64
Baud Rate Generator RB2/SDO/RX/DT Pin Buffer and Control Data Recovery RX9 or / 16
MSb STOP (8) 7
RSR Register *** 1
LSb 0 START
8 SPEN
RX9 ADDEN RX9 ADDEN RSR<8>
Enable Load of Receive Buffer 8
RX9D
RCREG Register FIFO
8 Interrupt RCIF RCIE Data Bus
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FIGURE 11-7:
RB2/SDO/RX/DT pin Load RSR Bit 8 = 0, Data Byte Read Bit 8 = 1, Address Byte Word 1 RCREG
ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT
START bit bit 0 bit 1 bit 8 STOP bit START bit bit 0 bit 8 STOP bit
RCIF
Note:
This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN = 1.
FIGURE 11-8:
RB2/SDO/RX/DT pin
ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST
START bit bit 0 bit 1 bit 8 STOP bit START bit bit 0 bit 8 STOP bit
Load RSR Bit 8 = 1, Address Byte Read Bit 8 = 0, Data Byte Word 1 RCREG
RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0.
TABLE 11-9:
Address
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF Bit 3 RBIE SSPIF Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x Value on all other RESETS 0000 000u -000 0000 0000 000x 0000 0000 -000 0000 0000 -010 0000 0000
Name
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
TMR2IF TMR1IF -000 0000 OERR RX9D 0000 000x 0000 0000
CREN ADDEN TXIE SYNC SSPIE --
USART Receive Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE -000 0000 0000 -010 0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented locations read as `0'. Shaded cells are not used for asynchronous reception.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 107
PIC16F87/88
11.3 USART Synchronous Master Mode
Clearing enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. The DT and CK pins will revert to highimpedance. If either bit CREN or bit SREN is set during a transmission, the transmission is aborted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from Highimpedance Receive mode to transmit and start driving. To avoid this, bit TXEN should be cleared. In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG can result in an immediate transfer of the data to the TSR register (if the TSR is empty). If the TSR was empty and the TXREG was written before writing the "new" TX9D, the "present" value of bit TX9D is loaded. Steps to follow when setting up a synchronous master transmission: 1. Initialize the SPBRG register for the appropriate baud rate (Section 11.1 "USART Baud Rate Generator (BRG)"). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RB5/SS/TX/CK and RB2/SDO/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).
11.3.1
USART SYNCHRONOUS MASTER TRANSMISSION
The USART transmitter block diagram is shown in Figure 11-6. The heart of the transmitter is the Transmit (Serial) Shift Register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCYCLE), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on the next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 11-9). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 11-10). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock immediately. Normally, when transmission is first started, the TSR register is empty, so a transfer to the TXREG register will result in an immediate transfer to TSR, resulting in an empty TXREG. Back-to-back transfers are possible.
2. 3. 4. 5. 6. 7. 8.
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TABLE 11-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
Address Name Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR 0000 000x -000 0000 0000 -00x 0000 0000 CCP1IE TMR2IE TMR1IE -000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other RESETS 0000 000u -000 0000 0000 -00x 0000 0000 -000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
USART Transmit Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master transmission.
FIGURE 11-9:
SYNCHRONOUS TRANSMISSION
Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 Q2 Q3 Q4
RB2/SDO/ RX/DT pin RB5/SS/TX/ CK pin Write to TXREG Reg TXIF bit (Interrupt Flag) TRMT bit `1'
bit 0
bit 1
bit 2
bit 7
bit 0
bit 1
bit 7
Word 1
Word 2
Write Word 1
Write Word 2
TXEN bit
`1'
Note: Sync Master mode; SPBRG = 0. Continuous transmission of two 8-bit words.
FIGURE 11-10:
SYNCHRONOUS TRANSMISSION (THROUGH TXEN)
bit 0 bit 1 bit 2 bit 6 bit 7
RB2/SDO/RX/DT pin RB5/SS/TX/CK pin
Write to TXREG Reg
TXIF bit
TRMT bit
TXEN bit
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 109
PIC16F87/88
11.3.2 USART SYNCHRONOUS MASTER RECEPTION
Once Synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RB2/SDO/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit, RCIF (PIR1<5>), is set. The actual interrupt can be enabled/disabled by setting/ clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read-only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double-buffered register (i.e., it is a two-deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then Overrun Error bit, OERR (RCSTA<1>), is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG, in order not to lose the old RX9D information. When setting up a synchronous master reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 11.1 "USART Baud Rate Generator (BRG)"). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit, RCIF, will be set when reception is complete and an interrupt will be generated if enable bit, RCIE, was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
TABLE 11-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Address Name Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF -- SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF TMR1IF RX9D Value on: POR, BOR 0000 000x -000 0000 0000 -00x 0000 0000 CCP1IE TMR2IE TMR1IE -000 0000 BRGH TRMT TX9D 0000 -010 0000 0000 Value on all other RESETS 0000 000u -000 0000 0000 -00x 0000 0000 -000 0000 0000 -010 0000 0000
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
USART Receive Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous master reception.
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FIGURE 11-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB2/SDO/RX/DT pin RB5/SS/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit (Interrupt) Read RXREG `0'
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
`0'
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0.
11.4
USART Synchronous Slave Mode
e)
Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RB5/SS/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).
If enable bit TXIE is set, the interrupt will wake the chip from SLEEP and if the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
When setting up a synchronous slave transmission, follow these steps: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.
11.4.1
USART SYNCHRONOUS SLAVE TRANSMIT
The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be set.
2. 3. 4. 5. 6. 7. 8.
TABLE 11-12: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Address Name Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 TMR0IF Bit 1 INTF Bit 0 R0IF Value on: POR, BOR 0000 000x Value on all other RESETS 0000 000u
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 19h 8Ch 98h 99h Legend: PIR1 RCSTA TXREG PIE1 TXSTA SPBRG
CCP1IF TMR2IF TMR1IF -000 0000 -000 0000 FERR OERR RX9D 0000 000x 0000 000x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 BRGH TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000
USART Transmit Register
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave transmission.
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Preliminary
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11.4.2 USART SYNCHRONOUS SLAVE RECEPTION
When setting up a synchronous slave reception, follow these steps: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h).
2. 3. 4. 5.
6.
7. 8. 9.
TABLE 11-13: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Address Name Bit 7 GIE -- SPEN -- CSRC Bit 6 PEIE ADIF RX9 ADIE TX9 Bit 5 TMR0IE RCIF SREN RCIE TXEN Bit 4 INTE TXIF CREN TXIE SYNC Bit 3 RBIE SSPIF ADDEN SSPIE -- Bit 2 TMR0IF CCP1IF FERR Bit 1 INTF TMR2IF OERR Bit 0 R0IF Value on: POR, BOR 0000 000x Value on all other RESETS 0000 000u
0Bh, 8Bh, INTCON 10Bh,18Bh 0Ch 18h 1Ah 8Ch 98h 99h Legend: PIR1 RCSTA RCREG PIE1 TXSTA SPBRG
TMR1IF -000 0000 -000 0000 RX9D 0000 000x 0000 000x 0000 0000 0000 0000
USART Receive Register BRGH TRMT TX9D
CCP1IE TMR2IE TMR1IE -000 0000 -000 0000 0000 -010 0000 -010 0000 0000 0000 0000
Baud Rate Generator Register
x = unknown, - = unimplemented, read as `0'. Shaded cells are not used for synchronous slave reception.
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Preliminary
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12.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE
The A/D module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) Analog Select Register (ANSEL)
The Analog-to-Digital (A/D) converter module has seven inputs for 18/20 pin devices (PIC16F88 devices only). The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has a high and low voltage reference input that is software selectable to some combination of VDD, VSS, VREF- (RA2), or VREF+ (RA3). The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator.
The ADCON0 register, shown in Register 12-2, controls the operation of the A/D module. The ANSEL register, shown in Register 12-1 and the ADCON1 register, shown in Register 12-3, configure the functions of the port pins. The port pins can be configured as analog inputs (RA3/RA2 can also be voltage references) or as digital I/O. Additional information on using the A/D module can be found in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
REGISTER 12-1:
ANSEL REGISTER (ADDRESS 9Bh) PIC16F88 DEVICES ONLY
U-0 -- bit 7 R/W-1 ANS6 R/W-1 ANS5 R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0 bit 0
bit 7 bit 6-0
Unimplemented: Read as `0' ANS<6:0>: Analog Input Select bits Bits select input function on corresponding AN<6:0> pins. 1 = Analog I/O (see notes below) 0 = Digital I/O Note 1: Setting a pin to an analog input disables the digital input buffer. The corresponding TRIS bit should be set to input mode when using pins as analog inputs. Only AN2 is an analog I/O, all other ANx pins are analog inputs. 2: See the block diagrams for the analog I/O pins to see how ANSEL interacts with the CHS bits of the ADCON0 register. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
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REGISTER 12-2: ADCON0 REGISTER (ADDRESS 1Fh) PIC16F88 DEVICES ONLY
R/W-0 ADCS1 bit 7 bit 7-6 ADCS<1:0>: A/D Conversion Clock Select bits If ADSC2 = 0: 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from the internal A/D module RC oscillator) If ADSC2 = 1: 00 = FOSC/4 01 = FOSC/16 10 = FOSC/64 11 = FRC (clock derived from the internal A/D module RC oscillator) CHS<2:0>: Analog Channel Select bits 000 = Channel 0 (RA0/AN0) 001 = Channel 1 (RA1/AN1) 010 = Channel 2 (RA2/AN2) 011 = Channel 3 (RA3/AN3) 100 = Channel 4 (RA4/AN4) 101 = Channel 5 (RB6/AN5) 110 = Channel 6 (RB7/AN6) GO/DONE: A/D Conversion Status bit If ADON = 1: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D conversion is complete) Unimplemented: Read as `0' ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut-off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown R/W-0 ADCS0 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE U-0 -- R/W-0 ADON bit 0
bit 5-3
bit 2
bit 1 bit 0
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REGISTER 12-3: ADCON1 REGISTER (ADDRESS 9Fh) PIC16F88 DEVICES ONLY
R/W-0 ADFM bit 7 bit 7 R/W-0 ADCS2 R/W-0 VCFG1 R/W-0 VCFG0 U-0 -- U-0 -- U-0 -- U-0 -- bit 0
ADFM: A/D Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are read as `0'. 0 = Left justified. Six Least Significant bits of ADRESL are read as `0'. ADCS2: A/D Clock Divide by 2 Select bit 1 = A/D clock source is divided by 2 when system clock is used 0 = Disabled VCFG<1:0>: A/D Voltage Reference Configuration bits Logic State
00 01 10 11
bit 6
bit 5-4
VREF+
AVDD AVDD
VREFAVSS
VREFAVSS
VREF+ VREF+
VREF-
Note: bit 3-0
The ANSEL bits for AN3 and AN2 inputs must be configured as analog inputs for the VREF+ and VREF- external pins to be used.
Unimplemented: Read as `0' Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 115
PIC16F87/88
The ADRESH:ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared, and A/D Interrupt Flag bit, ADIF, is set. The block diagram of the A/D module is shown in Figure 12-1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as inputs. To determine sample time, see Section 12.1. After this sample time has elapsed, the A/D conversion can be started. These steps should be followed for doing an A/D conversion: 1. Configure the A/D module: * Configure analog/digital I/O (ANSEL) * Configure voltage reference (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON0) * Turn on A/D module (ADCON0) 6. 7. 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * SET PEIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared (with interrupts disabled); OR * Waiting for the A/D interrupt Read A/D Result register pair (ADRESH:ADRESL), clear bit ADIF if required. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2 TAD is required before the next acquisition starts.
3. 4. 5.
FIGURE 12-1:
A/D BLOCK DIAGRAM
CHS2:CHS0
110 101 100
RB7/AN6/PGD/T1OSI RB6/AN5/PGC/T1OSO/T1CKI RA4/AN4/T0CKI/C2OUT
011
RA3/AN3/VREF+/C1OUT
010 VIN (Input Voltage) AVDD VREF+ (Reference Voltage) VCFG1:VCFG0 001
RA1/AN1 RA2/AN2/CVREF/VREF-
000
A/D Converter
RA0/AN0
VREF(Reference Voltage) AVSS VCFG1:VCFG0
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12.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 12-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 12-2. The maximum recommended impedance for analog sources is 2.5 k. As the impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 12-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. To calculate the minimum acquisition time, TACQ, see the PICmicro(R) Mid-Range Reference Manual (DS33023).
EQUATION 12-1:
TACQ
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = = = = = = = TAMP + TC + TCOFF 2 s + TC + [(Temperature -25C)(0.05 s/C)] CHOLD (RIC + RSS + RS) In(1/2047) -120 pF (1 k + 7 k + 10 k) In(0.0004885) 16.47 s 2 s + 16.47 s + [(50C - 25C)(0.05 s/C) 19.72 s
TC
TACQ
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again. During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 12-2:
ANALOG INPUT MODEL
VDD VT = 0.6V RIC 1k Sampling Switch SS RSS CHOLD = DAC capacitance = 51.2 pF VSS Legend: CPIN = input capacitance = threshold voltage VT I leakage = leakage current at the pin due to various junctions = interconnect resistance RIC SS = sampling switch CHOLD = sample/hold capacitance (from DAC)
Rs
ANx
VA
CPIN 5 pF
VT = 0.6V
I leakage 500 nA
6V 5V VDD 4 V 3V 2V
5 6 7 8 9 10 11 Sampling Switch (k)
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12.2 Selecting the A/D Conversion Clock 12.3 Configuring Analog Port Pins
The ADCON1, ANSEL, TRISA, and TRISB registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS<2:0> bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin that is defined as a digital input (including the RA4:RA0 and RB7:RB6 pins), may cause the input buffer to consume current out of the device specification.
The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: * * * * * * * 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC Internal A/D module RC oscillator (2-6 s)
For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time as small as possible, but no less than 1.6 s and not greater than 6.4 s. Table 12-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected.
TABLE 12-1:
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES - STANDARD DEVICES (C)
AD Clock Source (TAD) Maximum Device Frequency ADCS<1:0> 00 00 01 01 10 10 11 Max. 1.25 MHz 2.5 MHz 5 MHz 10 MHz 20 MHz 20 MHz (Note 1)
Operation 2 TOSC 4 TOSC 8 TOSC 16 TOSC 32 TOSC 64 TOSC RC Note 1: 2: 3:
(1,2,3)
ADCS<2> 0 1 0 1 0 1 X
The RC source has a typical TAD time of 4 s, but can vary between 2-6 s. When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only recommended for SLEEP operation. For extended voltage devices (LF), please refer to Section 18.0 "Electrical Characteristics".
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12.4 A/D Conversions
12.4.1 A/D RESULT REGISTERS
Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2 TAD wait is required before the next acquisition is started. After this 2 TAD wait, acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. In Figure 12-3, after the GO bit is set, the first time segment has a minimum of TCY and a maximum of TAD. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16 bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 12-4 shows the operation of the A/D result justification. The extra bits are loaded with `0's. When an A/D result will not overwrite these locations (A/D disable), these registers may be used as two general purpose 8-bit registers.
FIGURE 12-3:
A/D CONVERSION TAD CYCLES
TAD2 b9 Conversion starts TAD3 b8 TAD4 b7 TAD5 b6 TAD6 b5 TAD7 b4 TAD8 b3 TAD9 TAD10 TAD11 b2 b1 b0
TCY to TAD TAD1
Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit
ADRES is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input
FIGURE 12-4:
A/D RESULT JUSTIFICATION
10-bit Result ADFM = 1 ADFM = 0
7 0000 00
2107
0
7
0765 0000 00
0
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result Right Justified
10-bit Result Left Justified
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12.5 A/D Operation During SLEEP 12.6 Effects of a RESET
The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set. When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set. Turning off the A/D places the A/D module in its lowest current consumption state. Note: For the A/D module to operate in SLEEP, the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE bit. A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted. All A/D input pins are configured as analog inputs. The value that is in the ADRESH:ADRESL registers is not modified for a Power-on Reset. The ADRESH:ADRESL registers will contain unknown data after a Power-on Reset.
12.7
Use of the CCP Trigger
An A/D conversion can be started by the "special event trigger" of the CCP module. This requires that the CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as `1011' and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/ DONE bit will be set, starting the A/D conversion and the Timer1 counter will be reset to zero. Timer1 is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving the ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), then the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 counter.
TABLE 12-2:
Address
REGISTERS/BITS ASSOCIATED WITH A/D
Bit 7 GIE -- -- Bit 6 PEIE ADIF ADIE Bit 5 TMR0IE RCIF RCIE Bit 4 INTE TXIF TXIE Bit 3 RBIE SSPIF SSPIE Bit 2 TMR0IF CCP1IF CCP1IE Bit 1 INTF Bit 0 RBIF Value on POR, BOR Value on all other RESETS
Name
0Bh, 8Bh INTCON 10Bh, 18Bh 0Ch 8Ch 1Eh 9Eh 1Fh 9Fh 9Bh 05h PIR1 PIE1
0000 000x 0000 000u -000 0000 -000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
TMR2IF TMR1IF TMR2IE TMR1IE
ADRESH(1) A/D Result Register High Byte ADRESL(1) A/D Result Register Low Byte ADCON0(1)
(1)
ADCS1 ADCS0 ADCS2 AN6 RA6
CHS2 VCFG1 AN5 RA5
CHS1 VCFG0 AN4 RA4
CHS0 GO/DONE -- AN3 RA3 -- AN2 RA2
-- -- AN1 RA1
ADON -- AN0 RA0
0000 00-0 0000 00-0 0000 ---- 0000 ----111 1111 -111 1111 xxxx 0000 uuuu 0000 xxx0 0000 uuu0 0000
ADCON1(1) ADFM ANSEL -- RA7 PORTA (PIC16F87) (PIC16F88)
05h, 106h PORTB (PIC16F87) (PIC16F88) 85h Legend: Note 1: 2: TRISA 86h, 186h TRISB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx uuuu uuuu 00xx xxxx 00uu uuuu
TRISA7 TRISA6 TRISA5(2) PORTA Data Direction Register TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
1111 1111 1111 1111 1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used for A/D conversion. PIC16F88 only. Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'.
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13.0 COMPARATOR MODULE
The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA3 and RA4. The onchip Voltage Reference (Section 14.0 "Comparator Voltage Reference Module") can also be an input to the comparators. The CMCON register (Register 13-1) controls the comparator input and output multiplexers. A block diagram of the various comparator configurations is shown in Figure 13-1.
REGISTER 13-1:
CMCON REGISTER (ADDRESS 9Ch)
R-0 C2OUT bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-1 CM2 R/W-1 CM1 R/W-1 CM0 bit 0
bit 7
C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 1 = C2 VIN+ < C2 VIN0 = C2 VIN+ > C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 1 = C1 VIN+ < C1 VIN0 = C1 VIN+ > C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted CIS: Comparator Input Switch bit When CM2:CM0 = 001: 1 = C1 VIN- connects to RA3 0 = C1 VIN- connects to RA0 When CM2:CM0 = 010: 1 = C1 VIN- connects to RA3 C2 VIN- connects to RA2 0 = C1 VIN- connects to RA0 C2 VIN- connects to RA1 CM<2:0>: Comparator Mode bits Legend: R = Readable bit - n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4
bit 3
bit 2-0
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13.1 Comparator Configuration
Note: There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 13-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Section 18.0 "Electrical Characteristics". Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur.
FIGURE 13-1:
Comparators Reset CM2:CM0 = 000 RA0/AN0 RA3/AN3
A A
COMPARATOR I/O OPERATING MODES
Comparators Off (POR Default Value) CM2:CM0 = 111
VINVIN+
RA0/AN0 C1 Off (Read as `0') RA3/AN3
D D
VINVIN+
C1
Off (Read as `0')
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 Off (Read as `0') RA2/AN2
D D
VINVIN+
C2
Off (Read as `0')
Two Independent Comparators CM2:CM0 = 100 RA0/AN0 RA3/AN3
A A VINVIN+
Four Inputs Multiplexed to Two Comparators CM2:CM0 = 010 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+ A A CIS = 0 CIS = 1 VINVIN+
C1
C1OUT
RA3/AN3 RA1/AN1
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
C2
C2OUT
RA2/AN2
C2
C2OUT
From VREF Module Two Common Reference Comparators CM2:CM0 = 011 RA0/AN0 RA3/AN3
A D VINVIN+
Two Common Reference Comparators with Outputs CM2:CM0 = 110 RA0/AN0
A D VINVIN+
C1
C1OUT
RA3/AN3
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 C2OUT RA2/AN2 RA4/T0CKI
A A
VINVIN+
C2
C2OUT
One Independent Comparator CM2:CM0 = 101 RA0/AN0 RA3/AN3
D D VINVIN+
Three Inputs Multiplexed to Two Comparators CM2:CM0 = 001 RA0/AN0
A A CIS = 0 CIS = 1 VINVIN+
C1
Off (Read as `0')
RA3/AN3
C1
C1OUT
RA1/AN1 RA2/AN2
A A
VINVIN+
RA1/AN1 C2 C2OUT RA2/AN2
A A
VINVIN+
C2
C2OUT
A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch.
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13.2 Comparator Operation
13.3.2 INTERNAL REFERENCE SIGNAL
A single comparator is shown in Figure 13-2, along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 13-2 represent the uncertainty due to input offsets and response time. The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 14.0 "Comparator Voltage Reference Module" contains a detailed description of the Comparator Voltage Reference module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0> = 110 (Figure 13-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators.
13.3
Comparator Reference
13.4
Comparator Response Time
An external or internal reference signal may be used depending on the comparator operating mode. The analog signal present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 13-2).
FIGURE 13-2:
SINGLE COMPARATOR
Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise, the maximum delay of the comparators should be used (Section 18.0 "Electrical Characteristics").
VIN+ VIN-
+ -
Output
13.5
Comparator Outputs
VINVIN- VIN+ VIN+
The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When enabled, multiplexors in the output path of the RA3 and RA4 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 13-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/ disable for the RA3 and RA4 pins while in this mode. The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>).
Output Output
13.3.1
EXTERNAL REFERENCE SIGNAL
When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s).
Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input, according to the Schmitt Trigger input specification. 2: Analog levels, on any pin defined as a digital input, may cause the input buffer to consume more current than is specified.
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FIGURE 13-3: COMPARATOR OUTPUT BLOCK DIAGRAM
Port Pins
MULTIPLEX
CnINV
To Data Bus
Q EN RD_CMCON
D Q1
Set CMIF bit
Q
D EN CL Q3 * RD_CMCON
From other Comparator
NRESET
13.6
Comparator Interrupts
Note:
The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the comparator interrupt flag. The CMIF bit must be reset by clearing it (`0'). Since it is also possible to write a `1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs.
If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set.
The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.
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13.7 Comparator Operation During SLEEP 13.9 Analog Input Connection Considerations
When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional, if enabled. This interrupt will wake-up the device from SLEEP mode when enabled. While the comparator is powered up, higher SLEEP currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP. If the device wakes up from SLEEP, the contents of the CMCON register are not affected.
A simplified circuit for an analog input is shown in Figure 13-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current.
13.8
Effects of a RESET
A device RESET forces the CMCON register to its RESET state, causing the comparator module to be in the Comparator Off mode, CM<2:0> = 111.
FIGURE 13-4:
ANALOG INPUT MODEL
VDD RS < 10K AIN VT = 0.6V RIC
VA
CPIN 5 pF
VT = 0.6V
ILEAKAGE 500 nA
VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage
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TABLE 13-1:
Address 9Ch 9Dh
REGISTERS ASSOCIATED WITH THE COMPARATOR MODULE
Bit 7 C2OUT GIE OSFIF OSFIE RA7 Bit 6 C1OUT PEIE CMIF CMIE RA6 Bit 5 C2INV CVRR TMR0IE -- -- RA5 Bit 4 C1INV -- INTIE EEIF EEIE RA4 Bit 3 CIS CVR3 RBIE -- -- RA3 Bit 2 CM2 CVR2 TMR0IF -- -- RA2 Bit 1 CM1 CVR1 INTIF -- -- RA1 Bit 0 CM0 CVR0 RBIF -- -- RA0 xxxx 0000 uuuu 0000 xxx0 0000 uuu0 0000 TRISA7 TRISA6 TRISA5(1) TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111 Value on POR Value on all other RESETS
Name CMCON CVRCON
0000 0111 0000 0111 000- 0000 000- 0000 0000 000x 0000 000u 00-0 ---- 00-0 ---00-0 ---- 00-0 ----
CVREN CVROE
0Bh, 8Bh, INTCON 10Bh, 18Bh 0Dh 8Dh 05h PIR2 PIE2 PORTA (PIC16F87) (PIC16F88) TRISA
85h Legend: Note 1:
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are unused by the comparator module. Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read `1'.
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14.0 COMPARATOR VOLTAGE REFERENCE MODULE
supply voltage (also referred to as CVRSRC) comes directly from VDD. It should be noted, however, that the voltage at the top of the ladder is CVRSRC - VSAT, where VSAT is the saturation voltage of the power switch transistor. This reference will only be as accurate as the values of CVRSRC and VSAT. The output of the reference generator may be connected to the RA2/AN2/CVREF/VREF- pin. This can be used as a simple D/A function by the user, if a very high-impedance load is used. The primary purpose of this function is to provide a test path for testing the reference generator function.
The Comparator Voltage Reference Generator is a 16tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode `110'. A programmable register controls the function of the reference generator. Register 14-1 lists the bit functions of the CVRCON register. As shown in Figure 14-1, the resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The comparator reference
REGISTER 14-1:
CVRCON CONTROL REGISTER (ADDRESS 9Dh)
R/W-0 CVREN bit 7 R/W-0 CVROE R/W-0 CVRR U-0 -- R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 R/W-0 CVR0 bit 0
bit 7
CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the RA2/AN2/CVREF/VREF- pin 0 = CVREF voltage level is disconnected from the RA2/AN2/CVREF/VREF- pin CVRR: Comparator VREF Range Selection bit 1 = 0.00 CVRSRC to 0.75 CVRSRC with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC with CVRSRC/32 step size Unimplemented: Read as `0' CVR<3:0>: Comparator VREF Value Selection 0 VR3:VR0 15 bits When CVRR = 1: CVREF = (VR<3:0>/24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (VR3:VR0/32) * (CVRSRC) Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 6
bit 5
bit 4 bit 3-0
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FIGURE 14-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VDD
16 Stages CVREN 8R R R R R
8R
CVRR
RA2/AN2/CVREF/VREF- pin
CVROE CVREF Input to Comparator 16-1 Analog MUX CVR3 CVR2 CVR1 CVR0
TABLE 14-1:
Address 9Dh 9Ch Legend:
REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE
Bit 7 CVREN C2OUT Bit 6 CVROE C1OUT Bit 5 CVRR C2INV Bit 4 -- C1INV Bit 3 CVR3 CIS Bit 2 CVR2 CM2 Bit 1 CVR1 CM1 Bit 0 CVR0 CM0 Value on POR Value on all other RESETS
Name CVRCON CMCON
000- 0000 000- 0000 0000 0111 0000 0111
x = unknown, u = unchanged, - = unimplemented, read as `0'. Shaded cells are not used with the comparator voltage reference.
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PIC16F87/88
15.0 SPECIAL FEATURES OF THE CPU
SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up, or through an interrupt. Additional information on special features is available in the PICmicro(R) Mid-Range Reference Manual (DS33023).
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection: * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * Two-Speed Start-up * Fail-Safe Clock Monitor * SLEEP * Code Protection * ID Locations * In-Circuit Serial ProgrammingTM (ICSPTM) There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in RESET while the power supply stabilizes, and is enabled or disabled using a configuration bit. With these two timers on-chip, most applications need no external RESET circuitry.
15.1
Configuration Bits
The configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped in program memory locations 2007h and 2008h. The user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.
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REGISTER 15-1:
R/P-1 CP bit 13 bit 13 CP: FLASH Program Memory Code Protection bits 1 = Code protection off 0 = 0000h to 0FFFh code protected (All protected) CCPMX: CCP1 Pin Selection bit 1 = CCP1 function on RB0 0 = CCP1 function on RB3 DEBUG: In-Circuit Debugger Mode bit 1 = In-circuit debugger disabled, RB6 and RB7 are general purpose I/O pins 0 = In-circuit debugger enabled, RB6 and RB7 are dedicated to the debugger R/P-1
CONFIG1: CONFIGURATION WORD 1 REGISTER (ADDRESS 2007h)
R/P-1 R/P-1 R/P-1 R/P-1 CPD LVP R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 bit 0 BOREN MCLRE FOSC2 PWRTEN WDTEN FOSC1 FOSC0
R/P-1
CCPMX RESV WRT1 WRT0
bit 12
bit 11
bit 10-9 WRT<1:0>: FLASH Program Memory Write Enable bits 11 = Write protection off 10 = 0000h to 00FFh write protected, 0100h to 0FFFh may be modified by EECON control 01 = 0000h to 07FFh write protected, 0800h to 0FFFh may be modified by EECON control 00 = 0000h to 0FFFh write protected bit 8 CPD: Data EE Memory Code Protection bit 1 = Code protection off 0 = Data EE memory code protected LVP: Low-Voltage Programming Enable bit 1 = RB3/PGM pin has PGM function, low-voltage programming enabled 0 = RB3 is digital I/O, HV on MCLR must be used for programming BOREN: Brown-out Reset Enable bit 1 = BOR enabled 0 = BOR disabled MCLRE: RA5/MCLR Pin Function Select bit 1 = RA5/MCLR pin function is MCLR 0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD PWRTEN: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled
bit 7
bit 6
bit 5
bit 3
bit 2
bit 4, 1-0 FOSC<2:0>: Oscillator Selection bits 111 = EXTRC oscillator; CLKO function on RA6/OSC2/CLKO 110 = EXTRC oscillator; port I/O function on RA6/OSC2/CLKO 101 = INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin 100 = INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin 011 = EXTCLK; port I/O function on RA6/OSC2/CLKO 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
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REGISTER 15-2:
U-1 -- bit 13 bit 13-2 Unimplemented: Read as `1' bit 1 IESO: Internal External Switch Over bit 1 = Internal External Switch Over mode enabled 0 = Internal External Switch Over mode disabled FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor enabled 0 = Fail-Safe Clock Monitor disabled Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U-1 -- U-1 --
CONFIG2: CONFIGURATION WORD 2 REGISTER (ADDRESS 2008h)
U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- R/P-1 IESO R/P-1 FCMEN bit 0
bit 0
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15.2 RESET
The PIC16F87/88 differentiates between various kinds of RESET: * * * * * * Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset during normal operation WDT Wake-up during SLEEP Brown-out Reset (BOR) Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a "RESET state" on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT wake-up, which is viewed as the resumption of normal operation. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 15-3. These bits are used in software to determine the nature of the RESET. Upon a POR, BOR, or wake-up from SLEEP, the CPU requires approximately 5-10 s to become ready for code execution. This delay runs in parallel with any other timers. See Table 15-4 for a full description of RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 15-1.
FIGURE 15-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External RESET
MCLR WDT Module VDD Rise Detect VDD Brown-out Reset BOREN OST/PWRT OST 10-bit Ripple Counter OSC1 R Q Chip_Reset Power-on Reset S WDT SLEEP
Time-out Reset
PWRT INTRC 31.25 kHz 11-bit Ripple Counter
Enable PWRT Enable OST
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15.3 MCLR
PIC16F87/88 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin, that exceed its specification, can result in both MCLR and excessive current beyond the device specification during the ESD event. The circuit, as shown in Figure 15-2, is suggested. Note: For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. For more information, see Application Note, AN607 "Power-up Trouble Shooting" (DS00607).
15.5
Power-up Timer (PWRT)
The Power-up Timer (PWRT) of the PIC16F87/88 is a counter that uses the INTRC oscillator as the clock input. This yields a count of 72 ms. While the PWRT is counting, the device is held in RESET. The power-up time delay depends on the INTRC, and will vary from chip-to-chip due to temperature and process variation. See DC parameter #33 for details. The PWRT is enabled by clearing configuration bit PWRTEN.
The RA5/MCLR pin can be configured for MCLR (default), or as an I/O pin (RA5). This is configured through the MCLRE bit in Configuration Word 1.
FIGURE 15-2:
EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP)
VDD
15.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT delay is over (if enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset, or wake-up from SLEEP.
D
R R1 MCLR C PIC16F87/88
15.7
Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 = 1 k to 10 k will limit any current flowing into MCLR from external capacitor C (0.1 F), in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
Brown-out Reset (BOR)
The configuration bit, BOREN, can enable or disable the Brown-out Reset circuit. If VDD falls below VBOR (parameter D005, about 4V) for longer than TBOR (parameter #35, about 100 s), the brown-out situation will reset the device. If VDD falls below VBOR for less than TBOR, a RESET may not occur. Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer (if enabled) will keep the device in RESET for TPWRT (parameter #33, about 72 ms). If VDD should fall below VBOR during TPWRT, the Brownout Reset process will restart when VDD rises above VBOR, with the Power-up Timer Reset. Unlike previous PIC16 devices, the PWRT is no longer automatically enabled when the Brown-out Reset circuit is enabled. The PWRTEN and BOREN configuration bits are independent of each other.
15.4
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when VDD rise is detected (in the range of 1.2V-1.7V). To take advantage of the POR, tie the MCLR pin to VDD, as described in Section 15.3 "MCLR". A maximum rise time for VDD is specified. See Section 18.0 "Electrical Characteristics" for details.
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15.8 Time-out Sequence 15.9
On power-up, the time-out sequence is as follows: the PWRT delay starts (if enabled) when a POR occurs. Then, OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET. If MCLR is kept low long enough, all delays will expire. Bringing MCLR high will begin execution immediately. This is useful for testing purposes, or to synchronize more than one PIC16F87/88 device operating in parallel. Table 15-3 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 15-4 shows the RESET conditions for all the registers.
Power Control/Status Register (PCON)
The Power Control/Status Register, PCON, has two bits to indicate the type of RESET that last occurred. Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.
TABLE 15-1:
Oscillator Configuration XT, HS, LP EXTRC, INTRC T1OSC Note 1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up PWRTE = 0 TPWRT + 1024 * TOSC TPWRT -- PWRTE = 1 1024 * TOSC 5-10 s(1) -- Brown-out Reset PWRTE = 0 TPWRT + 1024 * TOSC TPWRT -- PWRTE = 1 1024 * TOSC 5-10 s(1) -- Wake-up from SLEEP 1024 * TOSC 5-10 s(1) 5-10 s(1)
CPU start-up is always invoked on POR, BOR and wake-up from SLEEP. The 5 s-10 s delay is based on a 1 MHz system clock.
TABLE 15-2:
POR 0 0 0 1 1 1 1 1
STATUS BITS AND THEIR SIGNIFICANCE
BOR x x x 0 1 1 1 1 TO 1 0 x 1 0 0 u 1 PD 1 x 0 1 1 0 u 0 Power-on Reset Illegal, TO is set on POR Illegal, PD is set on POR Brown-out Reset WDT Reset WDT Wake-up MCLR Reset during normal operation MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
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TABLE 15-3: RESET CONDITION FOR SPECIAL REGISTERS
Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt Wake-up from SLEEP Program Counter 000h 000h 000h 000h PC + 1 000h PC + 1(1) STATUS Register 0001 1xxx 000u uuuu 0001 0uuu 0000 1uuu uuu0 0uuu 0001 1uuu uuu1 0uuu PCON Register ---- --0x ---- --uu ---- --uu ---- --uu ---- --uu ---- --u0 ---- --uu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0' Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
TABLE 15-4:
Register W INDF TMR0 PCL STATUS FSR
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 1xxx xxxx xxxx xxxx 0000 xxx0 0000 xxxx xxxx 00xx xxxx ---0 0000 0000 000x -000 0000 00-0 ---xxxx xxxx xxxx xxxx -000 0000 0000 0000 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 0000 000x MCLR Reset, WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q quuu(3) uuuu uuuu uuuu 0000 uuu0 0000 uuuu uuuu 00uu uuuu ---0 0000 0000 000u -000 0000 00-0 ---uuuu uuuu uuuu uuuu -uuu uuuu 0000 0000 -000 0000 uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 0000 000x Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq quuu(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu(1) -uuu uuuu(1) uu-u ----(1) uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu
PORTA (PIC16F87) PORTA (PIC16F88) PORTB (PIC16F87) PORTB (PIC16F87) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 15-3 for RESET value for specific condition.
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TABLE 15-4:
Register TXREG RCREG ADRESH ADCON0 OPTION TRISA TRISB PIE1 PIE2 PCON OSCCON OSCTUNE PR2 SSPADD SSPSTAT TXSTA SPBRG ANSEL CMCON CVRCON WDTCON ADRESL ADCON1 EEDATA EEADR EEDATH EEADRH EECON1 EECON2
INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Power-on Reset, Brown-out Reset 0000 0000 0000 0000 xxxx xxxx 0000 00-0 1111 1111 1111 1111 1111 1111 -000 0000 00-0 ------- --qq -000 0000 --00 0000 1111 1111 0000 0000 0000 0000 0000 -010 0000 0000 -111 1111 0000 0111 000- 0000 ---0 1000 xxxx xxxx 0000 ---xxxx xxxx xxxx xxxx --xx xxxx ---- -xxx x--x x000 ---- ---MCLR Reset, WDT Reset 0000 0000 0000 0000 uuuu uuuu 0000 00-0 1111 1111 1111 1111 1111 1111 -000 0000 00-0 ------- --uu -000 0000 --00 0000 1111 1111 0000 0000 0000 0000 0000 -010 0000 0000 -111 1111 0000 0111 000- 0000 ---0 1000 uuuu uuuu 0000 ---uuuu uuuu uuuu uuuu --uu uuuu ---- -uuu u--x u000 ---- ---Wake-up via WDT or Interrupt uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uu-u ------- --uu -uuu uuuu --uu uuuu 1111 1111 uuuu uuuu uuuu uuuu uuuu -u1u uuuu uuuu -111 1111 uuuu u111 uuu- uuuu ---u uuuu uuuu uuuu uuuu ---uuuu uuuu uuuu uuuu --uu uuuu ---- -uuu u--u uuuu ---- ----
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as `0', q = value depends on condition, r = reserved, maintain clear Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 15-3 for RESET value for specific condition.
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FIGURE 15-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR)
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 15-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 15-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2
VDD
MCLR INTERNAL POR TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
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FIGURE 15-6: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V
15.10 Interrupts
The PIC16F87/88 has up to 12 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overflow interrupt flags are contained in the INTCON register. The peripheral interrupt flags are contained in the Special Function Register, PIR1. The corresponding interrupt enable bits are contained in Special Function Register, PIE1, and the peripheral interrupt enable bit is contained in Special Function Register, INTCON. When an interrupt is serviced, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack, and the PC is loaded with 0004h. Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends on when the interrupt event occurs, relative to the current Q cycle. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt's flag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on RESET. The "return from interrupt" instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.
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FIGURE 15-7:
EEIF EEIE OSFIF OSFIE ADIF ADIE RCIF RCIE TXIF TXIE SSPIF SSPIE CCP1IF CCP1IE TMR2IF TMR2IE TMR1IF TMR1IE CMIF CMIE TMR0IF TMR0IE INTF INTE RBIF RBIE PEIE GIE Wake-up (If in SLEEP mode)
INTERRUPT LOGIC
Interrupt to CPU
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15.10.1 INT INTERRUPT 15.10.3 PORTB INTCON CHANGE
External interrupt on the RB0/INT pin is edge-triggered, either rising, if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit, INTF (INTCON<1>), is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector, following wake-up. See Section 15.13 "Power-down Mode (SLEEP)" for details on SLEEP mode. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>), see Section 3.2 "EECON1 and EECON2 Registers".
15.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W, STATUS registers). Since the upper 16 bytes of each bank are common in the PIC16F87/88 devices, temporary holding registers W_TEMP, STATUS_TEMP, and PCLATH_TEMP should be placed in here. These 16 locations don't require banking and therefore, make it easier for context save and restore. The same code shown in Example 15-1 can be used.
15.10.2
TMR0 INTERRUPT
An overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON<5>), see Section 6.0 "Timer0 Module".
EXAMPLE 15-1:
MOVWF SWAPF CLRF MOVWF MOVF MOVWF CLRF : :(ISR) : MOVF MOVWF SWAPF MOVWF SWAPF SWAPF
SAVING STATUS, W, AND PCLATH REGISTERS IN RAM
;Copy ;Swap ;bank ;Save ;Only ;Save ;Page W to TEMP register status to be saved into W 0, regardless of current bank, Clears IRP,RP1,RP0 status to bank zero STATUS_TEMP register required if using page 1 PCLATH into W zero, regardless of current page
W_TEMP STATUS,W STATUS STATUS_TEMP PCLATH, W PCLATH_TEMP PCLATH
;(Insert user code here) PCLATH_TEMP, W PCLATH STATUS_TEMP,W STATUS W_TEMP,F W_TEMP,W ;Restore PCLATH ;Move W into PCLATH ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W
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15.12 Watchdog Timer (WDT)
For PIC16F87/88 devices, the WDT has been modified from previous PIC16 devices. The new WDT is code and functionally backward compatible with previous PIC16 WDT modules, and allows the user to have a scaler value for the WDT and TMR0 at the same time. In addition, the WDT time-out value can be extended to 268 seconds, using the prescaler with the postscaler when PSA is set to `1'.
15.12.2
WDT CONTROL
The WDTEN bit is located in Configuration Word 1 and when this bit is set, the WDT runs continuously. The SWDTEN bit is in the WDTCON register. When the WDTEN bit in the Configuration Word 1 register is set, the SWDTEN bit has no effect. If WDTEN is clear, then the SWDTEN bit can be used to enable and disable the WDT. Setting the bit will enable it and clearing the bit will disable it. The PSA and PS<2:0> bits (OPTION_REG) have the same function as in previous versions of the PIC16 family of microcontrollers.
15.12.1
WDT OSCILLATOR
The WDT derives its time base from the 31.25 kHz INTRC. The value of WDTCON is `---0 1000' on all RESETS. This gives a nominal time base of 16.38 ms, which is compatible with the time base generated with previous PIC16 microcontroller versions. Note: When the OST is invoked, the WDT is held in RESET, because the WDT ripple counter is used by the OST to perform the oscillator delay count. When the OST count has expired, the WDT will begin counting (if enabled).
A new prescaler has been added to the path between the internal RC and the multiplexors used to select the path for the WDT. This prescaler is 16 bits and can be programmed to divide the internal RC by 128 to 65536, giving the time base used for the WDT a nominal range of 1 ms to 2.097s.
FIGURE 15-8:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
0 Postscaler 16-bit Programmable Prescaler WDT 1 8 PSA
PS<2:0> TO TMR0 0 1 PSA
31.25 kHz INTRC Clock
WDTPS<3:0>
WDTEN from Configuration Word SWDTEN from WDTCON WDT Time-out
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TABLE 15-5:
WDTEN = 0 CLRWDT command Oscillator fail detected Exit SLEEP + System Clock = T1OSC, EXTRC, INTRC, EXTCLK Exit SLEEP + System Clock = XT, HS, LP Cleared at end of OST Cleared at end of OST Cleared Cleared
PRESCALER/POSTSCALER BIT STATUS
Conditions Prescaler Postscaler (PSA = 1)
REGISTER 15-3:
WDTCON REGISTER (ADDRESS 105h)
U-0 -- bit 7 U-0 -- U-0 -- R/W-0 WDTPS3 R/W-1 R/W-0 R/W-0 R/W-0 WDTPS2 WDTPS1 WDTPS0 SWDTEN(1) bit 0
bit 7-5 bit 4-1
Unimplemented: Read as `0' WDTPS<3:0>: Watchdog Timer Period Select bits Bit Prescale Value Rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16394 1010 = 1:32768 1011 = 1:65536 SWDTEN: Software Enable/Disable for Watchdog Timer bit(1) 1 = WDT is turned on 0 = WDT is turned off Note 1: If WDTEN configuration bit = 1, then WDT is always enabled, irrespective of this control bit. If WDTEN configuration bit = 0, then it is possible to turn WDT on/off with this control bit. Legend: R = Readable bit -n = Value at POR W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown
bit 0
TABLE 15-6:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name Bit 7 RBPU LVP -- Bit 6 INTEDG BOREN -- Bit 5 T0CS MVCLRE -- Bit 4 T0SE FOSC2 Bit 3 PSA PWRTEN Bit 2 PS2 WDTEN Bit 1 PS1 FOSC1 Bit 0 PS0 FOSC0
81h,181h OPTION 2007h 105h Configuration bits WDTCON
WDTPS3 WDTPS2 WSTPS1 WDTPS0 SWDTEN
Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Register 15-1 for operation of these bits.
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15.12.3 TWO-SPEED CLOCK START-UP MODE
Two-Speed Start-up mode minimizes the latency between oscillator start-up and code execution that may be selected with the IESO (Internal/External Switch Over) bit in Configuration Word 2. This mode is achieved by initially using the INTRC for code execution until the primary oscillator is stable. If this mode is enabled, and any of the following conditions exist, the system will begin execution with the INTRC oscillator. This results in almost immediate code execution with a minimum of delay. * POR and after the Power-up Timer has expired (if PWRTEN = 0), * or following a wake-up from SLEEP, * or a RESET when running from T1OSC or INTRC (after a RESET, SCS<1:0> are always set to `00'). Note: Following any RESET, the IRCF bits are zeroed and the frequency selection is forced to 31.25 kHz. The user can modify the IRCF bits to select a higher internal oscillator frequency. Checking the state of the OSTS bit will confirm whether the primary clock configuration is engaged. If not, the OSTS bit will remain clear. When the device is auto-configured in INTRC mode following a POR or wake-up from SLEEP, the rules for entering other oscillator modes still apply, meaning the SCS<1:0> bits in OSCCON can be modified before the OST time-out has occurred. This would allow the application to wake-up from SLEEP, perform a few instructions using the INTRC as the clock source and go back to SLEEP without waiting for the primary oscillator to become stable. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit to remain clear.
15.12.3.1
1. 2. 3. 4. 5. 6. 7. 8.
Two-Speed Start-up Mode Sequence
If the primary oscillator is configured to be anything other than XT, LP, or HS, then Two-Speed Start-up mode is disabled, because the primary oscillator will not require any time to become stable after POR, or an exit from SLEEP. If the IRCF bits of the OSCCON register are configured to a non-zero value prior to entering SLEEP mode, the system clock frequency will come from the output of the INTOSC. The IOFS bit in the OSCCON register will be clear until the INTOSC is stable. This will allow the user to determine when the internal oscillator can be used for time critical applications.
Wake-up from SLEEP, RESET, or POR. OSCON bits configured to run from INTRC (31.25 kHz). Instructions begin execution by INTRC (31.25 kHz). OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of INTRC. OSTS is set. System clock held low for eight falling edges of new clock (LP, XT, or HS). System clock is switched to primary source (LP, XT, or HS).
The software may read the OSTS bit to determine when the switch over takes place so that any software timing edges can be adjusted.
FIGURE 15-9:
TWO-SPEED START-UP MODE
CPU Start-up Q1 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
INTRC OSC1 TOST OSC2 System Clock SLEEP OSTS Program Counter PC 0000h 0001h 0003h 0004h 0005h
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15.12.4 FAIL-SAFE OPTION
The Fail-Safe Clock Monitor (FSCM) is designed to allow the device to continue to operate even in the event of an oscillator failure. The FSCM sample clock is generated by dividing the INTRC clock by 64. This will allow enough time between FSCM sample clocks for a system clock edge to occur. On the rising edge of the postscaled clock, the monitoring latch (CM = 0) will be cleared. On a falling edge of the primary or secondary system clock, the monitoring latch will be set (CM = 1). In the event that a falling edge of the postscaled clock occurs, and the monitoring latch is not set, a clock failure has been detected. While in Fail-Safe mode, a RESET will exit the failsafe condition. If the primary clock source is configured for a crystal, the OST timer will wait for the 1024 clock cycles for the OST time-out, and the device will continue running from the internal oscillator until the OST is complete. A SLEEP instruction, or a write to the SCS bits (where SCS bits do not = 00), can be performed to put the device into a low-power mode. Note: Two-Speed Start-up mode is automatically enabled when the fail-safe option is enabled.
FIGURE 15-10:
FSCM BLOCK DIAGRAM
Clock Monitor Latch (CM) (edge-triggered)
Peripheral Clock
S
Q
INTRC Oscillator 31.25 kHz (32 s)
/ 64 488 Hz (2.048 ms)
C
Q
Clock Failure Detected
The FSCM function is enabled by setting the FCMEN bit in Configuration Word 2. In the event of an oscillator failure, the FSCM will generate an oscillator fail interrupt and will switch the system clock over to the internal oscillator. The system will continue to come from the internal oscillator until the fail-safe condition is exited. The fail-safe condition is exited with either a RESET, the execution of a SLEEP instruction or a write to the OSCCON register. The frequency of the internal oscillator will depend upon the value contained in the IRCF bits. Another clock source can be selected via the IRCF and the SCS bits of the OSCCON register.
If RESET occurs while in Fail-Safe mode and the primary clock source is EC, or RC, then the device will immediately switch back to EC or RC mode.
15.12.4.1
Fail-Safe in Low-power Mode
A write to the OSCCON register, or SLEEP instruction will end the fail-safe condition. The system clock will default to the source selected by the SCS bits, which is either T1OSC, INTRC, or none (SLEEP mode). However, the FSCM will continue to monitor the system clock. If the secondary clock fails, the device will immediately switch to the internal oscillator clock. If OSFIE is set, an interrupt will be generated.
FIGURE 15-11:
Sample Clock System Clock Output CM Output (Q)
FSCM TIMING DIAGRAM
Oscillator Failure
Failure Detected OSCFIF
CM Test Note:
CM Test
CM Test
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
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15.12.4.2 FSCM and the Watchdog Timer
2. CONDITIONS: After a POR (Power-on Reset), the device is running in Two-Speed Start-up mode. The crystal fails before the OST has expired. If a crystal fails during the OST period, a fail-safe condition will not be detected (OSFIF will not get set). OSTS = 0 SCS = 00 OSFIF = 0 USER ACTION: Check the OSTS bit. If it's clear and the OST should have expired at this point, then the user can assume the crystal has failed. The user should change the SCS bit to cause a clock switch which will also release the 10-bit ripple counter for WDT operation (if enabled). 3. CONDITIONS: The device is clocked from a crystal during normal operation and it fails. OSTS = 0 SCS = 00 OSFIF = 1 USER ACTION: Clear the OSFIF bit. Configure the SCS bits for a clock switch and the fail-safe condition will be cleared. Later, if the user decides to, the crystal can be re-tried for operation. If this is done, the OSTS bit should be monitored to determine if the crystal operates. When a clock failure is detected, SCS<1:0> will be forced to `10', which will reset the WDT (if enabled).
15.12.4.3
POR or Wake From Sleep
The FSCM is designed to detect oscillator failure at any point after the device has exited Power-on Reset (POR) or low-power SLEEP mode. When the primary system clock is EC, RC or INTRC modes, monitoring can begin immediately following these events. For Oscillator modes involving a crystal or resonator (HS, LP, or XT), the situation is somewhat different. Since the oscillator may require a start-up time considerably longer than the FSCM sample clock time, a false clock failure may be detected. To prevent this, the internal oscillator block is automatically configured as the system clock and functions until the primary clock is stable (the OST timer has timed out). This is identical to Two-Speed Start-up mode. Once the primary clock is stable, the INTRC returns to its role as the FSCM source. Note: The same logic that prevents false oscillator failure interrupts on PORT or wake from SLEEP, will also prevent the detection of the oscillator's failure to start at all following these events. This can be avoided by monitoring the OSTS bit and using a timing routine to determine if the oscillator is taking too long to start. Even so, no oscillator failure interrupt will be flagged.
15.12.4.4
1.
Example Fail-Safe Conditions
15.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or high-impedance). For lowest current consumption in this mode, place all I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down the A/D and disable external clocks. Pull all I/O pins that are hi-impedance inputs, high or low externally, to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or VSS for lowest current consumption. The contribution from on-chip pull-ups on PORTB should also be considered. The MCLR pin must be at a logic high level (VIHMC).
CONDITIONS: The device is clocked from a crystal, crystal operation fails and then SLEEP mode is entered. OSTS = 0 SCS = 00 OSFIF = 1 USER ACTION: SLEEP mode will exit the fail-safe condition. Therefore, if the user code did not handle the detected fail-safe prior to the SLEEP command, then upon wake-up, the device will try to start the crystal that failed and a fail-safe condition will not be detected. Monitoring the OSTS bit will determine if the crystal is operating. The user should not enter SLEEP mode without handling the fail-safe condition first.
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15.13.1 WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a peripheral interrupt. interrupt enable bit must be set (enabled). Wake-up occurs regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.
External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and cause a "wake-up". The TO and PD bits in the STATUS register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if a WDT time-out occurred and caused wake-up. The following peripheral interrupts can wake the device from SLEEP: 1. 2. 3. 4. 5. 6. 7. 8. 9. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. CCP Capture mode interrupt. Special event trigger (Timer1 in Asynchronous mode using an external clock). SSP (START/STOP) bit detect interrupt. SSP transmit or receive in Slave mode (SPI/I2C). A/D conversion (when A/D clock source is RC). EEPROM write operation completion. Comparator output changes state. USART RX or TX (Synchronous Slave mode).
15.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If the interrupt occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will not be cleared, the TO bit will not be set and the PD bit will not be cleared. * If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from SLEEP. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT prescaler and postscaler (if enabled) will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction.
Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding
FIGURE 15-12:
OSC1 CLKO(4) INT pin INTF Flag (INTCON<1>) GIE bit(3) (INTCON<7>) INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT(1)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 TOST(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Interrupt Latency (Note 2) Processor in SLEEP
PC+1 Inst(PC + 1) SLEEP
PC+2
PC+2 Inst(PC + 2) Inst(PC + 1)
PC + 2
0004h Inst(0004h)
0005h Inst(0005h) Inst(0004h)
Inst(PC) = SLEEP Inst(PC - 1)
Dummy Cycle
Dummy Cycle
XT, HS or LP Oscillator mode assumed. TOST = 1024 TOSC (drawing not to scale). This delay will not be there for RC Osc mode. GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line. CLKO is not available in these Osc modes, but shown here for timing reference.
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15.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a `0', the In-Circuit Debugger functionality is enabled. This function allows simple debugging functions when used with MPLAB(R) ICD. When the microcontroller has this feature enabled, some of the resources are not available for general use. Table 15-7 shows which features are consumed by the background debugger.
15.17 In-Circuit Serial Programming
PIC16F87/88 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see Figure 15-13 for an example). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For more information on serial programming, please refer to the PIC16F87/88 Programming Specification (DS39607).
TABLE 15-7:
I/O pins Stack
DEBUGGER RESOURCES
RB6, RB7 1 level Address 0000h must be NOP Last 100h words 0x070 (0x0F0, 0x170, 0x1F0) 0x1EB-0x1EF
Program Memory Data Memory
FIGURE 15-13:
TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
To Normal Connections
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial Programming connections to MCLR/VPP, VDD, GND, RB7 and RB6. This will interface to the In-Circuit Debugger module available from Microchip, or one of the third party development tool companies.
External Connector Signals +5V 0V VPP CLK Data I/O RB3/PGM
*
PIC16F87/88 VDD VSS MCLR/VPP RB6 RB7 RB3
15.15 Program Verification/Code Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes.
15.16 ID Locations
Four memory locations (2000h - 2003h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the four Least Significant bits of the ID location are used. * * *
VDD To Normal Connections * Isolation devices (as required). RB3 only used in LVP mode.
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15.18 Low-Voltage ICSP Programming
The LVP bit of the configuration word enables lowvoltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD source in the operating voltage range. This only means that VPP does not have to be brought to VIHH, but can instead be left at the normal operating voltage. In this mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O pin. If Low-Voltage Programming mode is not used, the LVP bit can be programmed to a `0' and RB3/PGM becomes a digital I/O pin. However, the LVP bit may only be programmed when programming mode is entered with VIHH on MCLR. The LVP bit can only be changed when using high voltage on MCLR. It should be noted that once the LVP bit is programmed to `0', only the High-Voltage Programming mode is available and only this mode can be used to program the device. When using Low-Voltage ICSP, the part must be supplied at 4.5V to 5.5V if a bulk erase will be executed. This includes reprogramming of the code protect bits from an on-state to an off-state. For all other cases of LowVoltage ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique user IDs, or user code can be reprogrammed or added. The following LVP steps assume the LVP bit is set in the Configuration register. 1. 2. 3. 4. 5. Apply VDD to the VDD pin. Drive MCLR low. Apply VDD to the RB3/PGM pin. Apply VDD to the MCLR pin. Follow with the associated programming steps. Note 1: The High-Voltage Programming mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR pin. 2: While in Low-Voltage ICSP mode (LVP = 1), the RB3 pin can no longer be used as a general purpose I/O pin. 3: When using Low-Voltage ICSP Programming (LVP) and the pull-ups on PORTB are enabled, bit 3 in the TRISB register must be cleared to disable the pull-up on RB3 and ensure the proper operation of the device. 4: RB3 should not be allowed to float if LVP is enabled. An external pull-down device should be used to default the device to normal operating mode. If RB3 floats high, the PIC16F87/88 device will enter Programming mode. 5: LVP mode is enabled by default on all devices shipped from Microchip. It can be disabled by clearing the LVP bit in the CONFIG register. 6: Disabling LVP will provide maximum compatibility to other PIC16CXXX devices.
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16.0 INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: * Byte-oriented operations * Bit-oriented operations * Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. The formats for each of the categories are presented in Figure 16-1, while the various opcode fields are summarized in Table 16-1. Table 16-2 lists the instructions recognized by the MPASMTM assembler. A complete description of each instruction is also available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023). For byte-oriented instructions, `f' represents a file register designator and `d' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If `d' is zero, the result is placed in the W register. If `d' is one, the result is placed in the file register specified in the instruction. For bit-oriented instructions, `b' represents a bit field designator, which selects the bit affected by the operation, while `f' represents the address of the file in which the bit is located. For literal and control operations, `k' represents an eight or eleven-bit constant or literal value One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 s. All instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Note: To maintain upward compatibility with future PIC16F87/88 products, do not use the OPTION and TRIS instructions. For example, a "clrf PORTB" instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared.
TABLE 16-1:
Field
f W b k x
OPCODE FIELD DESCRIPTIONS
Description
Register file address (0x00 to 0x7F) Working register (accumulator) Bit address within an 8-bit file register Literal field, constant data or label Don't care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. Program Counter Time-out bit Power-down bit
d
PC TO PD
FIGURE 16-1:
GENERAL FORMAT FOR INSTRUCTIONS
0
Byte-oriented file register operations 13 876 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 76 OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE k = 8-bit immediate value 8 7 k (literal)
0
All instruction examples use the format `0xhh' to represent a hexadecimal number, where `h' signifies a hexadecimal digit.
0
16.1
READ-MODIFY-WRITE OPERATIONS
CALL and GOTO instructions only 13 11 OPCODE 10 k (literal) 0
Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator `d'. A read operation is performed on a register even if the instruction writes to that register.
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TABLE 16-2:
Mnemonic, Operands
PIC16F87/88 INSTRUCTION SET
Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, b f, b f, b f, b k k k k k k k k k Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 1 2 1 2 1 1 2 2 2 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff C,DC,Z Z Z Z Z Z Z Z Z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2
C C C,DC,Z Z
1,2 1,2 1,2 1,2 1,2 1,2 1,2 3 3
BIT-ORIENTED FILE REGISTER OPERATIONS 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff C,DC,Z Z TO,PD Z
LITERAL AND CONTROL OPERATIONS 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk
TO,PD C,DC,Z Z
2: 3:
When an I/O register is modified as a function of itself (e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is `1' for a pin configured as input and is driven low by an external device, the data will be written back with a `0'. If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro(R) Mid-Range MCU Family Reference Manual (DS33023).
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16.2
ADDLW Syntax: Operands: Operation: Status Affected: Description:
Instruction Descriptions
Add Literal and W [ label ] ADDLW 0 k 255 (W) + k (W) C, DC, Z The contents of the W register are added to the eight-bit literal `k' and the result is placed in the W register. Operation: Status Affected: Description: k ANDWF Syntax: Operands: AND W with f [ label ] ANDWF 0 f 127 d [0,1] (W) .AND. (f) (destination) Z AND the W register with register `f'. If `d' = 0, the result is stored in the W register. If `d' = 1, the result is stored back in register `f'. f,d
ADDWF Syntax: Operands: Operation: Status Affected: Description:
Add W and f [ label ] ADDWF 0 f 127 d [0,1] (W) + (f) (destination) C, DC, Z Add the contents of the W register with register `f'. If `d' = 0, the result is stored in the W register. If `d' = 1, the result is stored back in register `f'. f,d
BCF Syntax: Operands: Operation: Status Affected: Description:
Bit Clear f [ label ] BCF 0 f 127 0b7 0 (f) None Bit `b' in register `f' is cleared. f,b
ANDLW Syntax: Operands: Operation: Status Affected: Description:
AND Literal with W [ label ] ANDLW 0 k 255 (W) .AND. (k) (W) Z The contents of W register are AND'ed with the eight-bit literal `k'. The result is placed in the W register. k
BSF Syntax: Operands: Operation: Status Affected: Description:
Bit Set f [ label ] BSF 0 f 127 0b7 1 (f) None Bit `b' in register `f' is set. f,b
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BTFSS Syntax: Operands: Operation: Status Affected: Description: Bit Test f, Skip if Set [ label ] BTFSS f,b 0 f 127 0b<7 skip if (f) = 1 None If bit `b' in register `f' = 0, the next instruction is executed. If bit `b' = 1, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction. Status Affected: Description: CLRF Syntax: Operands: Operation: Clear f [ label ] CLRF 0 f 127 00h (f) 1Z Z The contents of register `f' are cleared and the Z bit is set. f
BTFSC Syntax: Operands: Operation: Status Affected: Description:
Bit Test, Skip if Clear [ label ] BTFSC f,b 0 f 127 0b7 skip if (f) = 0 None If bit `b' in register `f' = 1, the next instruction is executed. If bit `b', in register `f', = 0, the next instruction is discarded, and a NOP is executed instead, making this a 2 TCY instruction.
CLRW Syntax: Operands: Operation: Status Affected: Description:
Clear W [ label ] CLRW None 00h (W) 1Z Z W register is cleared. Zero bit (Z) is set.
CALL Syntax: Operands: Operation:
Call Subroutine [ label ] CALL k 0 k 2047 (PC) + 1 TOS, k PC<10:0>, (PCLATH<4:3>) PC<12:11> None Call subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a two-cycle instruction.
CLRWDT Syntax: Operands: Operation:
Clear Watchdog Timer [ label ] CLRWDT None 00h WDT 0 WDT prescaler, 1 TO 1 PD TO, PD CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set.
Status Affected: Description:
Status Affected: Description:
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COMF Syntax: Operands: Operation: Status Affected: Description: Complement f [ label ] COMF 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are complemented. If `d' = 0, the result is stored in W. If `d' = 1, the result is stored back in register `f'. Status Affected: Description: f,d GOTO Syntax: Operands: Operation: Unconditional Branch [ label ] GOTO k 0 k 2047 k PC<10:0> PCLATH<4:3> PC<12:11> None GOTO is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a two-cycle instruction.
DECF Syntax: Operands: Operation: Status Affected: Description:
Decrement f [ label ] DECF f,d 0 f 127 d [0,1] (f) - 1 (destination) Z Decrement register `f'. If `d' = 0, the result is stored in the W register. If `d' = 1, the result is stored back in register `f'.
INCF Syntax: Operands: Operation: Status Affected: Description:
Increment f [ label ] INCF f,d 0 f 127 d [0,1] (f) + 1 (destination) Z The contents of register `f' are incremented. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is placed back in register `f'.
DECFSZ Syntax: Operands: Operation: Status Affected: Description:
Decrement f, Skip if 0 [ label ] DECFSZ f,d 0 f 127 d [0,1] (f) - 1 (destination); skip if result = 0 None The contents of register `f' are decremented. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', then a NOP is executed instead, making it a 2 TCY instruction.
INCFSZ Syntax: Operands: Operation: Status Affected: Description:
Increment f, Skip if 0 [ label ] INCFSZ f,d 0 f 127 d [0,1] (f) + 1 (destination), skip if result = 0 None The contents of register `f' are incremented. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is placed back in register `f'. If the result is `1', the next instruction is executed. If the result is `0', a NOP is executed instead, making it a 2 TCY instruction.
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IORLW Syntax: Operands: Operation: Status Affected: Description: Inclusive OR Literal with W [ label ] IORLW k 0 k 255 (W) .OR. k (W) Z The contents of the W register are OR'd with the eight-bit literal `k'. The result is placed in the W register. MOVLW Syntax: Operands: Operation: Status Affected: Description: Move Literal to W [ label ] k (W) None The eight-bit literal `k' is loaded into W register. The don't cares will assemble as `0's. MOVLW k 0 k 255
IORWF Syntax: Operands: Operation: Status Affected: Description:
Inclusive OR W with f [ label ] IORWF f,d 0 f 127 d [0,1] (W) .OR. (f) (destination) Z Inclusive OR the W register with register `f'. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is placed back in register `f'.
MOVWF Syntax: Operands: Operation: Status Affected: Description:
Move W to f [ label ] (W) (f) None Move data from W register to register `f'. MOVWF f 0 f 127
MOVF Syntax: Operands: Operation: Status Affected: Description:
Move f [ label ] MOVF f,d 0 f 127 d [0,1] (f) (destination) Z The contents of register `f' are moved to a destination dependant upon the status of `d'. If `d' = 0, the destination is W register. If `d' = 1, the destination is file register `f' itself. `d' = 1 is useful to test a file register, since status flag Z is affected.
NOP Syntax: Operands: Operation: Status Affected: Description:
No Operation [ label ] None No operation None No operation. NOP
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RETFIE Syntax: Operands: Operation: Status Affected: Return from Interrupt [ label ] None TOS PC, 1 GIE None RETFIE RLF Syntax: Operands: Operation: Status Affected: Description: Rotate Left f through Carry [ label ] RLF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the left through the Carry Flag. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is stored back in register `f'.
C Register f
RETLW Syntax: Operands: Operation: Status Affected: Description:
Return with Literal in W [ label ] RETLW k 0 k 255 k (W); TOS PC None The W register is loaded with the eight-bit literal `k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.
RRF Syntax: Operands: Operation: Status Affected: Description:
Rotate Right f through Carry [ label ] RRF f,d 0 f 127 d [0,1] See description below C The contents of register `f' are rotated one bit to the right through the Carry Flag. If `d' = 0, the result is placed in the W register. If `d' = 1, the result is placed back in register `f'.
C Register f
RETURN Syntax: Operands: Operation: Status Affected: Description:
Return from Subroutine [ label ] None TOS PC None Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. RETURN
SLEEP Syntax: Operands: Operation: [ label ] None 00h WDT, 0 WDT prescaler, 1 TO, 0 PD TO, PD The power-down status bit, PD is cleared. Time-out status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. SLEEP
Status Affected: Description:
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SUBLW Syntax: Operands: Operation: Description: Subtract W from Literal [ label ] SUBLW k 0 k 255 k - (W) (W) The W register is subtracted (2's complement method) from the eight-bit literal `k'. The result is placed in the W register. XORLW Syntax: Operands: Operation: Status Affected: Description: Exclusive OR Literal with W [ label ] XORLW k
0 k 255 (W) .XOR. k (W) Z The contents of the W register are XOR'ed with the eight-bit literal `k'. The result is placed in the W register.
Status Affected: C, DC, Z
SUBWF Syntax: Operands: Operation: Description:
Subtract W from f [ label ] SUBWF f,d 0 f 127 d [0,1] (f) - (W) (destination) Subtract (2's complement method) W register from register `f'. If `d' = 0, the result is stored in the W register. If `d' = 1, the result is stored back in register `f'.
XORWF Syntax: Operands: Operation: Status Affected: Description:
Exclusive OR W with f [ label ] XORWF 0 f 127 d [0,1] (W) .XOR. (f) (destination) Z Exclusive OR the contents of the W register with register `f'. If `d' = 0, the result is stored in the W register. If `d' = 1, the result is stored back in register `f'. f,d
Status Affected: C, DC, Z
SWAPF Syntax: Operands: Operation: Status Affected: Description:
Swap Nibbles in f [ label ] SWAPF f,d 0 f 127 d [0,1] (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) None The upper and lower nibbles of register `f' are exchanged. If `d' = 0, the result is placed in W register. If `d' = 1, the result is placed in register `f'.
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17.0 DEVELOPMENT SUPPORT
17.1
The PICmicro(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB C30 C Compiler - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator - MPLAB dsPIC30 Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB ICE 4000 In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Development Programmer * Low-cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM.netTM Demonstration Board - PICDEM 2 Plus Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 4 Demonstration Board - PICDEM 17 Demonstration Board - PICDEM 18R Demonstration Board - PICDEM LIN Demonstration Board - PICDEM USB Demonstration Board * Evaluation Kits - KEELOQ(R) - PICDEM MSC - microID(R) - CAN - PowerSmart(R) - Analog
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) based application that contains: * An interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) * A full-featured editor with color coded context * A multiple project manager * Customizable data windows with direct edit of contents * High level source code debugging * Mouse over variable inspection * Extensive on-line help The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PICmicro emulator and simulator tools (automatically updates all project information) * Debug using: - source files (assembly or C) - absolute listing file (mixed assembly and C) - machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increasing flexibility and power.
17.2
MPASM Assembler
The MPASM assembler is a full-featured, universal macro assembler for all PICmicro MCUs. The MPASM assembler generates relocatable object files for the MPLINK object linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM assembler features include: * Integration into MPLAB IDE projects * User defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process
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17.3 MPLAB C17 and MPLAB C18 C Compilers 17.6 MPLAB ASM30 Assembler, Linker, and Librarian
The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
MPLAB ASM30 assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 compiler uses the assembler to produce it's object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
17.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian manages the creation and modification of library files of pre-compiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction
17.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC hosted environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until Break, or Trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and MPLAB C18 C Compilers, as well as the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool.
17.5
MPLAB C30 C Compiler
17.8
MPLAB SIM30 Software Simulator
The MPLAB C30 C compiler is a full-featured, ANSI compliant, optimizing compiler that translates standard ANSI C programs into dsPIC30F assembly language source. The compiler also supports many commandline options and language extensions to take full advantage of the dsPIC30F device hardware capabilities, and afford fine control of the compiler code generator. MPLAB C30 is distributed with a complete ANSI C standard library. All library functions have been validated and conform to the ANSI C library standard. The library includes functions for string manipulation, dynamic memory allocation, data conversion, timekeeping, and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high level source debugging with the MPLAB IDE.
The MPLAB SIM30 software simulator allows code development in a PC hosted environment by simulating the dsPIC30F series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. The MPLAB SIM30 simulator fully supports symbolic debugging using the MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines.
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17.9 MPLAB ICE 2000 High-performance Universal In-Circuit Emulator 17.11 MPLAB ICD 2 In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the FLASH PICmicro MCUs and can be used to develop for these and other PICmicro microcontrollers. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers cost effective in-circuit FLASH debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PICmicro devices.
The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
17.12 PRO MATE II Universal Device Programmer
The PRO MATE II is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features an LCD display for instructions and error messages and a modular detachable socket assembly to support various package types. In Stand-Alone mode, the PRO MATE II device programmer can read, verify, and program PICmicro devices without a PC connection. It can also set code protection in this mode.
17.10 MPLAB ICE 4000 High-performance Universal In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICD 4000 is a premium emulator system, providing the features of MPLAB ICE 2000, but with increased emulation memory and high-speed performance for dsPIC30F and PIC18XXXX devices. Its advanced emulator features include complex triggering and timing, up to 2 Mb of emulation memory, and the ability to view variables in real time. The MPLAB ICE 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.
17.13 PICSTART Plus Development Programmer
The PICSTART Plus development programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports most PICmicro devices up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant.
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17.14 PICDEM 1 PICmicro Demonstration Board
The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The sample microcontrollers provided with the PICDEM 1 demonstration board can be programmed with a PRO MATE II device programmer, or a PICSTART Plus development programmer. The PICDEM 1 demonstration board can be connected to the MPLAB ICE in-circuit emulator for testing. A prototype area extends the circuitry for additional application components. Features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs.
17.17 PICDEM 3 PIC16C92X Demonstration Board
The PICDEM 3 demonstration board supports the PIC16C923 and PIC16C924 in the PLCC package. All the necessary hardware and software is included to run the demonstration programs.
17.18 PICDEM 4 8/14/18-Pin Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8-, 14-, and 18-pin PIC16XXXX and PIC18XXXX MCUs, including the PIC16F818/819, PIC16F87/88, PIC16F62XA and the PIC18F1320 family of microcontrollers. PICDEM 4 is intended to showcase the many features of these low pin count parts, including LIN and Motor Control using ECCP. Special provisions are made for low-power operation with the supercapacitor circuit, and jumpers allow on-board hardware to be disabled to eliminate current draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, DB-9 RS-232 interface, ICD connector for programming via ICSP and development with MPLAB ICD 2, 2x16 liquid crystal display, PCB footprints for H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User's Guide.
17.15 PICDEM.net Internet/Ethernet Demonstration Board
The PICDEM.net demonstration board is an Internet/ Ethernet demonstration board using the PIC18F452 microcontroller and TCP/IP firmware. The board supports any 40-pin DIP device that conforms to the standard pinout used by the PIC16F877 or PIC18C452. This kit features a user friendly TCP/IP stack, web server with HTML, a 24L256 Serial EEPROM for Xmodem download to web pages into Serial EEPROM, ICSP/MPLAB ICD 2 interface connector, an Ethernet interface, RS-232 interface, and a 16 x 2 LCD display. Also included is the book and CD-ROM "TCP/IP Lean, Web Servers for Embedded Systems," by Jeremy Bentham
17.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756A, PIC17C762 and PIC17C766. A programmed sample is included. The PRO MATE II device programmer, or the PICSTART Plus development programmer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion.
17.16 PICDEM 2 Plus Demonstration Board
The PICDEM 2 Plus demonstration board supports many 18-, 28-, and 40-pin microcontrollers, including PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers provided with the PICDEM 2 demonstration board can be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or MPLAB ICD 2 with a Universal Programmer Adapter. The MPLAB ICD 2 and MPLAB ICE in-circuit emulators may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area extends the circuitry for additional application components. Some of the features include an RS-232 interface, a 2 x 16 LCD display, a piezo speaker, an on-board temperature sensor, four LEDs, and sample PIC18F452 and PIC16F877 FLASH microcontrollers.
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17.20 PICDEM 18R PIC18C601/801 Demonstration Board
The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/De-multiplexed and 16-bit Memory modes. The board includes 2 Mb external FLASH memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
17.23 PICDEM USB PIC16C7X5 Demonstration Board
The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers. This board provides the basis for future USB products.
17.24 Evaluation and Programming Tools
In addition to the PICDEM series of circuits, Microchip has a line of evaluation kits and demonstration software for these products. * KEELOQ evaluation and programming tools for Microchip's HCS Secure Data Products * CAN developers kit for automotive network applications * Analog design boards and filter design software * PowerSmart battery charging evaluation/ calibration kits * IrDA(R) development kit * microID development and rfLabTM development software * SEEVAL(R) designer kit for memory evaluation and endurance calculations * PICDEM MSC demo boards for Switching mode power supply, high-power IR driver, delta sigma ADC, and flow rate sensor Check the Microchip web page and the latest Product Line Card for the complete list of demonstration and evaluation kits.
17.21 PICDEM LIN PIC16C43X Demonstration Board
The powerful LIN hardware and software kit includes a series of boards and three PICmicro microcontrollers. The small footprint PIC16C432 and PIC16C433 are used as slaves in the LIN communication and feature on-board LIN transceivers. A PIC16F874 FLASH microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.
17.22 PICkitTM 1 FLASH Starter Kit
A complete "development system in a box", the PICkit FLASH Starter Kit includes a convenient multi-section board for programming, evaluation, and development of 8/14-pin FLASH PIC(R) microcontrollers. Powered via USB, the board operates under a simple Windows GUI. The PICkit 1 Starter Kit includes the user's guide (on CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB(R) IDE (Integrated Development Environment) software, software and hardware "Tips 'n Tricks for 8-pin FLASH PIC(R) Microcontrollers" Handbook and a USB Interface Cable. Supports all current 8/14-pin FLASH PIC microcontrollers, as well as many future planned devices.
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18.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V Voltage on MCLR with respect to VSS (Note 2) .............................................................................................-0.3 to +14V Total power dissipation (Note 1) ..................................................................................................................................1W Maximum current out of VSS pin ...........................................................................................................................200 mA Maximum current into VDD pin ..............................................................................................................................200 mA Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by PORTA ........................................................................................................................100 mA Maximum current sourced by PORTA...................................................................................................................100 mA Maximum current sunk by PORTB........................................................................................................................100 mA Maximum current sourced by PORTB ..................................................................................................................100 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD - VOH) x IOH} + (VOl x IOL) 2: Voltage spikes at the MCLR pin may cause latch-up. A series resistor of greater than 1 k should be used to pull MCLR to VDD, rather than tying the pin directly to VDD. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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FIGURE 18-1: PIC16F87/88 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
16 MHz
20 MHz
Frequency
FIGURE 18-2:
PIC16LF87/88 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V 5.0V
Voltage
4.5V 4.0V 3.5V 3.0V 2.5V 2.0V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
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18.1 DC Characteristics: Supply Voltage PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Characteristic Supply Voltage PIC16LF87/88 PIC16F87/88 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Brown-out Reset Voltage PIC16LF87/88 PIC16F87/88 3.65 3.65 -- -- 4.35 4.35 V V FMAX = 14 MHz(2) 2.0 4.0 1.5 -- -- -- -- -- 5.5 5.5 -- 0.7 V V V V See Section 15.4 "Power-on Reset (POR)" for details See Section 15.4 "Power-on Reset (POR)" for details HS, XT, RC and LP Osc mode Min Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No. Symbol VDD D001 D001 D002 D003
D004
SVDD
0.05
--
--
V/ms
VBOR D005 D005 Legend: Note 1: 2:
Shading of rows is to assist in readability of the table. This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data. When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
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18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Power-down Current (IPD)(1) PIC16LF87/88 0.1 0.1 0.4 PIC16LF87/88 0.3 0.3 0.7 All devices 0.6 0.6 1.2 Legend: Note 1: 0.4 0.4 1.5 0.5 0.5 1.7 1.0 1.0 5.0 A A A A A A A A A -40C 25C 85C -40C 25C 85C -40C 25C 85C VDD = 5.0V VDD = 3.0V VDD = 2.0V Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS30487B-page 166
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2,3) PIC16LF87/88 9 7 7 PIC16LF87/88 16 14 14 All devices 32 26 26 PIC16LF87/88 72 76 76 PIC16LF87/88 138 136 136 All devices 310 290 280 PIC16LF87/88 270 280 285 PIC16LF87/88 460 450 450 All devices 900 890 890 Legend: Note 1: 20 15 15 30 25 25 40 35 35 95 90 90 175 170 170 380 360 360 315 310 310 610 600 600 1060 1050 1050 A A A A A A A A A A A A A A A A A A A A A A A A A A A -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC Oscillator)(3) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHZ (RC Oscillator)(3) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 32 kHZ (LP Oscillator) VDD = 2.0V Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 167
PIC16F87/88
18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2,3) All devices 1.8 1.6 1.3 All devices 3.0 2.5 2.5 Legend: Note 1: 2.3 2.2 2.2 4.2 4.0 4.0 mA mA mA mA mA mA -40C 25C 85C -40C 25C 85C VDD = 5.0V VDD = 4.0V FOSC = 20 MHZ (HS Oscillator) Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS30487B-page 168
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2,3) PIC16LF87/88 8 7 7 PIC16LF87/88 16 14 14 All devices 32 29 29 PIC16LF87/88 132 126 126 PIC16LF87/88 260 230 230 All devices 560 500 500 PIC16LF87/88 310 300 300 PIC16LF87/88 550 530 530 All devices 1.2 1.1 1.1 Legend: Note 1: 20 15 15 30 25 25 40 35 35 160 155 155 310 300 300 690 650 650 420 410 410 650 620 620 1.5 1.4 1.4 A A A A A A A A A A A A A A A A A A A A A A A A mA mA mA -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C 25C 85C VDD = 5.0V VDD = 3.0V FOSC = 4 MHz (RC_RUN mode, Internal RC Oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 1 MHz (RC_RUN mode, Internal RC Oscillator) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 31.25 kHz (RC_RUN mode, Internal RC Oscillator) VDD = 2.0V Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 169
PIC16F87/88
18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Supply Current (IDD)(2,3) PIC16LF87/88 .950 .930 .930 All devices 1.8 1.7 1.7 PIC16LF87/88 9 9 11 PIC16LF87/88 12 12 14 All devices 20 20 25 Legend: Note 1: 1.3 1.2 1.2 3.0 2.8 2.8 13 14 16 34 31 28 72 65 59 mA mA mA mA mA mA A A A A A A A A A -40C 25C 85C -40C 25C 85C -10C 25C 70C -10C 25C 70C -10C 25C 70C VDD = 5.0V VDD = 3.0V FOSC = 32 kHz (SEC_RUN mode, Timer1 as clock) VDD = 2.0V VDD = 5.0V VDD = 3.0V FOSC = 8 MHz (RC_RUN mode, Internal RC Oscillator) Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
DS30487B-page 170
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
18.2 DC Characteristics: Power-down and Supply Current PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Typ Max Units Conditions
PIC16LF87/88 (Industrial) PIC16F87/88 (Industrial) Param No.
Module Differential Currents (IWDT, IBOR, ILVD, IOSCB, IAD) D022 (IWDT) Watchdog Timer 1.5 2.2 2.7 2.3 2.7 3.1 3.0 3.3 3.9 D022A (IBOR) D025 (IOSCB) Brown-out Reset Timer1 Oscillator 40 1.7 1.8 2.0 2.2 2.6 2.9 3.0 3.2 3.4 D026 (IAD) A/D Converter 0.001 0.001 0.003 Legend: Note 1: 3.8 3.8 4.0 4.6 4.6 4.8 10.0 10.0 13.0 60 2.3 2.3 2.3 3.8 3.8 3.8 6.0 6.0 7.0 2.0 2.0 2.0 A A A A A A A A A A A A A A A A A A A A A A -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C to +85C -40C 25C 85C -40C 25C 85C -40C 25C 85C -40C to +85C -40C to +85C -40C to +85C VDD = 2.0V VDD = 3.0V VDD = 5.0V A/D on, not converting VDD = 5.0V VDD = 3.0V 32 kHz on Timer1 VDD = 2.0V VDD = 5.0V VDD = 5.0V VDD = 3.0V VDD = 2.0V
2:
3:
Shading of rows is to assist in readability of the table. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, etc.). The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT enabled/disabled as specified. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 171
PIC16F87/88
18.3 DC Characteristics: Internal RC Accuracy PIC16F87/88 (Industrial) PIC16LF87/88 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Device Min Typ Max Units Conditions
PIC16LF87/88
(Industrial)
PIC16F87/88
(Industrial) Param No.
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1) PIC16LF87/88 -2 -5 -10 PIC16F87/88 -2 -5 -10 INTRC Accuracy @ Freq = 31 kHz PIC16LF87/88 PIC16F87/88 Legend: Note 1: 2:
(2)
1 -- -- 1 -- -- -- --
2 5 10 2 5 10 35.938 35.938
% % % % % % kHz kHz
25C -10C - +85C -40C - +85C 25C -10C - +85C -40C - +85C -40C - +85C -40C - +85C
VDD = 2.7-3.3V VDD = 2.7-3.3V VDD = 2.7-3.3V VDD = 4.5-5.5V VDD = 4.5-5.5V VDD = 4.5-5.5V VDD = 2.7-3.3V VDD = 4.5-5.5V
26.562 26.562
Shading of rows is to assist in readability of the table. Frequency calibrated at 25C. OSCTUNE register can be used to compensate for temperature drift. INTRC frequency after calibration.
DS30487B-page 172
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
18.4 DC Characteristics: PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 18.1 "DC Characteristics: Supply Voltage". Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Sym No. VIL D030 D030A D031 D032 D033
Characteristic Input Low Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR, OSC1 (in RC mode) OSC1 (in XT and LP mode) OSC1 (in HS mode) Ports RB1 and RB4:
VSS VSS VSS VSS VSS VSS VSS
-- -- -- -- -- -- --
0.15 VDD 0.8V 0.2 VDD 0.2 VDD 0.3V 0.3 VDD 0.3 VDD
V V V V V V V
For entire VDD range 4.5V VDD 5.5V (Note 1)
D034 VIH D040 D040A D041 D042 D042A D043 D044 D070 D060 D061 D063 IIL
with Schmitt Trigger buffer Input High Voltage I/O ports: with TTL buffer with Schmitt Trigger buffer MCLR OSC1 (in XT and LP mode) OSC1 (in HS mode) OSC1 (in RC mode) Ports RB1 and RB4: with Schmitt Trigger buffer IPURB PORTB Weak Pull-up Current Input Leakage Current (Notes 2, 3) I/O ports MCLR OSC1
For entire VDD range
2.0 0.25 VDD + 0.8V 0.8 VDD 0.8 VDD 1.6V 0.7 VDD 0.9 VDD 0.7 VDD 50 -- -- --
-- -- -- -- -- -- -- -- 250 -- -- --
VDD VDD VDD VDD VDD VDD VDD VDD 400 1 5 5
V V V V V V V V A A A A
4.5V VDD 5.5V For entire VDD range For entire VDD range
(Note 1) For entire VDD range VDD = 5V, VPIN = VSS Vss VPIN VDD, pin at high-impedance Vss VPIN VDD Vss VPIN VDD, XT, HS and LP osc configuration
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87/88 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 173
PIC16F87/88
18.4 DC Characteristics: PIC16F87/88 (Industrial, Extended) PIC16LF87/88 (Industrial) (Continued)
Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC Specification, Section 18.1 "DC Characteristics: Supply Voltage". Min Typ Max Units Conditions
DC CHARACTERISTICS
Param Sym No. VOL D080 D083 VOH D090 D092
Characteristic Output Low Voltage I/O ports OSC2/CLKO (RC osc configuration) Output High Voltage I/O ports (Note 3) OSC2/CLKO (RC osc configuration)
-- --
-- --
0.6 0.6
V V
IOL = 8.5 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +125C In XT, HS and LP modes when external clock is used to drive OSC1
VDD - 0.7 VDD - 0.7
-- --
-- --
V V
Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin -- -- 15 pF
D101 D102 D120 D121 D122 D130 D131 D132A D133 D134
CIO CB ED
All I/O pins and OSC2 (in RC mode) SCL, SDA in I2C mode Data EEPROM Memory Endurance
-- -- 100K 10K VMIN -- 10K 1K VMIN VMIN -- --
-- -- 1M 100K -- 4 100K 10K -- -- 2 2
50 400 -- -- 5.5 8 -- -- 5.5 5.5 4 4
pF pF E/W -40C to 85C E/W +85C to +125C V ms E/W -40C to 85C E/W +85C to +125C V V ms ms Using EECON to read/write, VMIN = min. operating voltage Using EECON to read/write, VMIN = min. operating voltage
VDRW VDD for read/write TDEW Erase/write cycle time Program FLASH Memory EP VPR Endurance VDD for read VDD for erase/write TPE TPW Erase cycle time Write cycle time
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PIC16F87/88 be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin.
DS30487B-page 174
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
TABLE 18-1: COMPARATOR SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C, unless otherwise stated. Param No. D300 D301 D302 300 300A 301 * Note 1: Characteristics Input Offset Voltage Input Common Mode Voltage* Response Time(1)* Comparator Mode Change to Output Valid* Sym VIOFF VICM TRESP TMC2OV Min -- 0 55 -- -- Typ 5.0 150 -- Max 10 VDD - 1.5 -- 400 600 10 Units mV V dB ns ns s PIC16F87/88 PIC16LF87/88 Comments
Common Mode Rejection Ratio* CMRR
These parameters are characterized but not tested. Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from VSS to VDD.
TABLE 18-2:
VOLTAGE REFERENCE SPECIFICATIONS
Operating Conditions: 3.0V < VDD < 5.5V, -40C < TA < +85C, unless otherwise stated. Spec No. D310 D311 D312 310 * Note 1: Characteristics Resolution Absolute Accuracy Unit Resistor Value (R)* Settling Time
(1)*
Sym VRES VRAA VRUR TSET
Min VDD/24 -- -- -- --
Typ -- -- -- 2k --
Max VDD/32 1/4 1/2 -- 10
Units LSb LSb LSb s
Comments
Low Range (VRR = 1) High Range (VRR = 0)
These parameters are characterized but not tested. Settling time measured while VRR = 1 and VR<3:0> transitions from `0000' to `1111'.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 175
PIC16F87/88
18.5 Timing Parameter Symbology
The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low I2C only AA BUF output access Bus free T Time 3. TCC:ST 4. Ts (I2C specifications only) (I2C specifications only)
osc rd rw sc ss t0 t1 wr
OSC1 RD RD or WR SCK SS T0CKI T1CKI WR
P R V Z High Low
Period Rise Valid High-impedance High Low
TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition
SU STO
Setup STOP condition
FIGURE 18-3:
LOAD CONDITIONS
Load Condition 1 VDD/2 Load Condition 2
RL
Pin VSS RL = 464 CL = 50 pF 15 pF
CL
Pin VSS
CL
for all pins except OSC2, but including PORTD and PORTE outputs as ports for OSC2 output
DS30487B-page 176
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
FIGURE 18-4: EXTERNAL CLOCK TIMING
Q4 Q1 Q2 Q3 Q4 Q1
OSC1 1 2 CLKO 3 3 4 4
TABLE 18-3:
Parameter No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym Characteristic External CLKI Frequency (Note 1) Min DC DC DC Oscillator Frequency (Note 1) DC 0.1 4 5 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- TCY -- -- -- -- -- -- Max 1 20 32 4 4 20 200 -- -- -- -- 10,000 250 -- DC -- -- -- 25 50 15 Units Conditions
FOSC
MHz XT and RC Osc mode MHz HS Osc mode kHz LP Osc mode MHz RC Osc mode MHz XT Osc mode MHz HS Osc mode kHz LP Osc mode ns ns ms ns ns ns ms ns ns ms ns ns ns ns XT and RC Osc mode HS Osc mode LP Osc mode RC Osc mode XT Osc mode HS Osc mode LP Osc mode TCY = 4/FOSC XT oscillator LP oscillator HS oscillator XT oscillator LP oscillator HS oscillator
1
TOSC
External CLKI Period (Note 1)
1000 50 5 250 250 50 5
Oscillator Period (Note 1)
2 3
TCY TosL, TosH
Instruction Cycle Time (Note 1) External Clock in (OSC1) High or Low Time
200 500 2.5 15 -- -- --
4
TosR, TosF
External Clock in (OSC1) Rise or Fall Time
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions, with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time limit is "DC" (no clock) for all devices.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 177
PIC16F87/88
FIGURE 18-5: CLKO AND I/O TIMING
Q4 OSC1 10 CLKO 13 14 I/O Pin (Input) 17 I/O Pin (Output) Old Value 15 New Value 19 18 12 16 11 Q1 Q2 Q3
20, 21 Note: Refer to Figure 18-3 for load conditions.
TABLE 18-4:
Param No. 10* 11* 12* 13* 14* 15* 16* 17* 18* Symbol TosH2ckL TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI
CLKO AND I/O TIMING REQUIREMENTS
Characteristic OSC1 to CLKO CLKO rise time CLKO fall time CLKO to Port out valid Port in valid before CLKO Port in hold after CLKO OSC1 (Q1 cycle) to Port out valid OSC1 (Q2 cycle) to Port input invalid (I/O in hold time) Port output rise time Port output fall time INT pin high or low time RB7:RB4 change INT high or low time PIC16F87/88 PIC16LF87/88 Min -- -- -- -- -- TOSC + 200 0 -- 100 200 0 -- -- -- -- TCY TCY Typ 75 75 35 35 -- -- -- 100 -- -- -- 10 -- 10 -- -- -- Max 200 200 100 100 0.5 TCY + 20 -- -- 255 -- -- -- 40 145 40 145 -- -- Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1)
TosH2ckH OSC1 to CLKO
19* 20* 21* 22* 23*
TioV2osH TIOR TIOF TINP TRBP *
Port input valid to OSC1 (I/O in setup time) PIC16F87/88 PIC16LF87/88 PIC16F87/88 PIC16LF87/88
Note 1:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. These parameters are asynchronous events not related to any internal clock edges. Measurements are taken in RC mode where CLKO output is 4 x TOSC.
DS30487B-page 178
Preliminary
2003 Microchip Technology Inc.
PIC16F87/88
FIGURE 18-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING
VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal RESET Watchdog Timer Reset 34 I/O Pins 32 30
31 34
Note: Refer to Figure 18-3 for load conditions.
FIGURE 18-7:
BROWN-OUT RESET TIMING
VDD
VBOR 35
TABLE 18-5:
Parameter No. 30 31*
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS
Sym Characteristic MCLR Pulse Width (Low) Watchdog Timer Time-out Period (16-bit prescaler = 0100 and no postscaler) Oscillation Start-up Timer Period Power-up Timer Period I/O High-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Min 2 TBD Typ -- 16 Max -- TBD Units s ms Conditions VDD = 5V, -40C to +85C VDD = 5V, -40C to +85C
TmcL TWDT
32 33* 34 35 *
TOST TPWRT TIOZ TBOR
-- TBD -- 100
1024 TOSC 72 -- --
-- TBD 2.1 --
-- ms s s
TOSC = OSC1 period VDD = 5V, -40C to +85C
VDD VBOR (D005)
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 179
PIC16F87/88
FIGURE 18-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI 40 42 41
RB6/T1OSO/T1CKI 45 47 TMR0 or TMR1 Note: Refer to Figure 18-3 for load conditions. 46 48
TABLE 18-6:
Param No. 40* 41* 42* Symbol Tt0H Tt0L Tt0P
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 TCY + 40 Greater of: 20 or TCY + 40 N 0.5 TCY + 20 15 25 30 50 0.5 TCY + 20 15 25 30 50 Greater of: 30 or TCY + 40 N Greater of: 50 or TCY + 40 N 60 100 DC 2 TOSC -- -- -- -- -- -- 32.768 7 TOSC ns ns kHz -- Typ -- -- -- -- -- -- Max -- -- -- -- -- -- Units ns ns ns ns ns ns N = prescale value (2, 4, ..., 256) Must also meet parameter 47 Conditions Must also meet parameter 42 Must also meet parameter 42
45*
Tt1H
T1CKI High Time
Synchronous, Prescaler = 1 Synchronous, PIC16F87/88 Prescaler = 2,4,8 PIC16LF87/88 Asynchronous PIC16F87/88 PIC16LF87/88
-- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- --
ns ns ns ns ns ns ns ns ns ns ns
46*
Tt1L
T1CKI Low Time
Synchronous, Prescaler = 1 Synchronous, PIC16F87/88 Prescaler = 2,4,8 PIC16LF87/88 Asynchronous PIC16F87/88 PIC16LF87/88 PIC16F87/88
Must also meet parameter 47
47*
Tt1P
T1CKI Input Period
Synchronous
N = prescale value (1, 2, 4, 8) N = prescale value (1, 2, 4, 8)
PIC16LF87/88
Asynchronous Ft1 48
PIC16F87/88 PIC16LF87/88
Timer1 Oscillator Input Frequency Range (Oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from External Clock Edge to Timer Increment *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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FIGURE 18-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1)
CCP1 (Capture Mode)
50 52
51
CCP1 (Compare or PWM Mode) 53 Note: Refer to Figure 18-3 for load conditions. 54
TABLE 18-7:
Param Symbol No. 50* TccL
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Characteristic CCP1 No Prescaler Input Low Time Min 0.5 TCY + 20 10 20 0.5 TCY + 20 10 20 3 TCY + 40 N PIC16F87/88 PIC16LF87/88 PIC16F87/88 PIC16LF87/88 -- -- -- -- Typ Max Units -- -- -- -- -- -- -- 10 25 10 25 -- -- -- -- -- -- -- 25 50 25 45 ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1,4 or 16) Conditions
PIC16F87/88 With Prescaler PIC16LF87/88 PIC16F87/88 With Prescaler PIC16LF87/88
51*
TccH
CCP1 No Prescaler Input High Time
52* 53* 54*
TccP TccR TccF
CCP1 Input Period CCP1 Output Rise Time CCP1 Output Fall Time
* These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F87/88
FIGURE 18-10:
SS 70 SCK (CKP = 0) 71 72
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 18-3 for load conditions. Bit 6 - - - -1
Bit 6 - - - - - -1
LSb
LSb In
FIGURE 18-11:
SS
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79
SDO
MSb 75, 76
Bit 6 - - - - - -1
LSb
SDI
MSb In 74
Bit 6 - - - -1
LSb In
Note: Refer to Figure 18-3 for load conditions.
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PIC16F87/88
FIGURE 18-12: SPI SLAVE MODE TIMING (CKE = 0)
SS 70 SCK (CKP = 0) 71 72 83
78
79
SCK (CKP = 1) 79 78
80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 18-3 for load conditions. Bit 6 - - - -1
Bit 6 - - - - - -1
LSb 77 LSb In
FIGURE 18-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK (CKP = 0)
70 83 71 72
SCK (CKP = 1) 80
SDO
MSb 75, 76
Bit 6 - - - - - -1
LSb 77
SDI
MSb In 74
Bit 6 - - - -1
LSb In
Note: Refer to Figure 18-3 for load conditions.
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TABLE 18-8:
Param No. 70* 71* 72* 73* 74* 75* 76* 77* 78* 79* 80* 81* 82* 83*
SPI MODE REQUIREMENTS
Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Setup time of SDI data input to SCK edge Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output high-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) SDO data output valid after SCK edge SDO data output setup to SCK edge SDO data output valid after SS edge SS after SCK edge PIC16F87/88 PIC16LF87/88 PIC16F87/88 PIC16LF87/88 PIC16F87/88 PIC16LF87/88 Min TCY TCY + 20 TCY + 20 100 100 -- -- -- 10 -- -- -- -- -- TCY -- 1.5 TCY + 40 Typ -- -- -- -- -- 10 25 10 -- 10 25 10 -- -- -- -- -- Max -- -- -- -- -- 25 50 25 50 25 50 25 50 145 -- 50 -- Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions
Symbol TssL2scH, TssL2scL TscH TscL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TdoV2scH, TdoV2scL TssL2doV TscH2ssH, TscL2ssH *
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 18-14:
I2C BUS START/STOP BITS TIMING
SCL 90 SDA
91 92
93
START Condition Note: Refer to Figure 18-3 for load conditions.
STOP Condition
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PIC16F87/88
TABLE 18-9:
Param No. 90* 91* 92* 93 *
I2C BUS START/STOP BITS REQUIREMENTS
Characteristic START condition Setup time START condition Hold time STOP condition Setup time STOP condition Hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min Typ Max Units 4700 -- 600 600 600 600 -- -- -- -- 4000 -- 4700 -- 4000 -- -- -- -- -- -- -- -- -- ns ns ns ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated
Symbol TSU:STA THD:STA TSU:STO THD:STO
These parameters are characterized but not tested.
FIGURE 18-15:
I2C BUS DATA TIMING
103 100 101 102
SCL
90 91
106
107 92
SDA In 110 109 SDA Out Note: Refer to Figure 18-3 for load conditions. 109
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TABLE 18-10: I2C BUS DATA REQUIREMENTS
Param. No. 100* Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101* TLOW Clock low time 100 kHz mode 400 kHz mode SSP Module 102* TR SDA and SCL rise time SDA and SCL fall time START condition setup time START condition hold time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 400 kHz mode 107* 92* 109* 110* TSU:DAT TSU:STO TAA TBUF Data input setup time STOP condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode CB * Note 1: 2: Bus capacitive loading Min 4.0 0.6 1.5 TCY 4.7 1.3 1.5 TCY -- 20 + 0.1 CB -- 20 + 0.1 CB 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 ns ns ns ns s s s s ns s ns ns s s ns ns s s pF Time the bus must be free before a new transmission can start (Note 1) (Note 2) CB is specified to be from 10 - 400 pF Only relevant for Repeated START condition After this period, the first clock pulse is generated CB is specified to be from 10 - 400 pF s s Units s s Conditions
103*
TF
90*
TSU:STA
91* 106*
THD:STA THD:DAT
Data input hold time 100 kHz mode
These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast mode (400 kHz) I2C bus device can be used in a standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line, TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification), before the SCL line is released.
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PIC16F87/88
FIGURE 18-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
RB5/TX/CK pin RB2/RX/DT pin
121 121
120 122 Note: Refer to Figure 18-3 for load conditions.
TABLE 18-11: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param No. 120 Sym TckH2dtV Characteristic SYNC XMIT (MASTER & SLAVE) Clock high to data out valid PIC16F87/88 -- PIC16LF87/88 -- -- -- -- -- -- -- -- -- -- -- 80 100 45 50 45 50 ns ns ns ns ns ns Min Typ Max Units Conditions
121 122
Tckrf Tdtrf
Clock out rise time and fall time PIC16F87/88 (Master mode) PIC16LF87/88 Data out rise time and fall time PIC16F87/88 PIC16LF87/88
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
FIGURE 18-17:
RB5/TX/CK pin RB2/RX/DT pin
USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
125
126 Note: Refer to Figure 18-3 for load conditions.
TABLE 18-12: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Param No. 125 126 Sym TdtV2ckL TckL2dtl Characteristic SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) Data hold after CK (DT hold time) Min Typ Max Units Conditions
15 15
-- --
-- --
ns ns
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
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PIC16F87/88
TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16F87/88 (INDUSTRIAL, EXTENDED) PIC16LF87/88 (INDUSTRIAL)
Param Sym No. A01 A03 A04 A06 A07 A10 A20 A21 A22 A25 A30 A50 NR EIL EDL EOFF EGN -- VREF Characteristic Resolution Integral linearity error Differential linearity error Offset error Gain error Monotonicity(3) Reference Voltage Min -- -- -- -- -- -- 2.5 2.2 AVDD - 2.5V AVSS - 0.3V VSS - 0.3V -- -- -- -- -- Typ -- -- -- -- -- guaranteed -- -- Max 10 bits <1 <1 <2 <1 -- VDD + 0.3 VDD + 0.3 AVDD + 0.3V VREF+ - 2.0V VREF + 0.3V 2.5 5 Units bit LSb LSb LSb LSb -- V V V V V k A See (Note 4) During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 12.1 "A/D Acquisition Requirements". During A/D Conversion cycle. Conditions VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VREF = VDD = 5.12V, VSS VAIN VREF VSS VAIN VREF -40C to +85C 0C to +85C
VREF+ Reference voltage high VREF- Reference voltage low VAIN ZAIN IREF Analog input voltage Recommended impedance of analog voltage source VREF input current(2)
-- Note 1: 2: 3:
--
500
A
Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. The maximum allowed impedance for analog voltage source is 10 k. This requires higher acquisition times.
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PIC16F87/88
FIGURE 18-18: A/D CONVERSION TIMING
1 TCY (TOSC/2)(1) Q4 130 A/D CLK A/D DATA ADRES ADIF GO SAMPLING STOPPED DONE 132 9 8 7 ... ... 2 1 0 NEW_DATA 131 BSF ADCON0, GO
OLD_DATA
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
TABLE 18-14: A/D CONVERSION REQUIREMENTS
Param No. 130 Sym TAD Characteristic A/D clock period PIC16F87/88 PIC16LF87/88 PIC16F87/88 PIC16LF87/88 131 132 TCNV TACQ Conversion time (not including S/H time) (Note 1) Acquisition time (Note 2) 10* Min 1.6 3.0 2.0 3.0 Typ -- -- 4.0 6.0 -- 40 -- Max -- -- 6.0 9.0 12 -- -- Units s s s s TAD s s Conditions TOSC based, VREF 3.0V TOSC based, VREF 2.0V A/D RC mode A/D RC mode
The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.
134
TGO
Q4 to A/D clock start
--
TOSC/2
--
--
* Note 1: 2:
These parameters are characterized but not tested. Data in "Typ" column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. ADRES register may be read on the following TCY cycle. See Section 12.1 "A/D Acquisition Requirements" for minimum conditions.
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NOTES:
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19.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES
No Graphs and Tables are available at this time.
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NOTES:
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20.0
20.1
PACKAGING INFORMATION
Package Marking Information
18-Lead PDIP
XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN
Example
PIC16F87/88-I/P 0310017
18-Lead SOIC
XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN
Example
PIC16F87/8804/SO 0310017
20-Lead SSOP
XXXXXXXXXXX XXXXXXXXXXX YYWWNNN
Example
PIC16F8720/SS 0310017
28-Lead QFN
Example
XXXXXXXX XXXXXXXX YYWWNNN
PIC16F87 -I/ML 0310017
Legend:
XX...X Y YY WW NNN
Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information.
*
Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.
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PIC16F87/88
18-Lead Plastic Dual In-line (P) - 300 mil (PDIP)
E1
D
2 n 1
E
A2 A L A1 B1
c
eB Units Dimension Limits n p
B
p
MIN
Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 Molded Package Width E1 .240 .250 .260 Overall Length D .890 .898 .905 Tip to Seating Plane L .125 .130 .135 c Lead Thickness .008 .012 .015 Upper Lead Width B1 .045 .058 .070 Lower Lead Width B .014 .018 .022 Overall Row Spacing eB .310 .370 .430 Mold Draft Angle Top 5 10 15 Mold Draft Angle Bottom 5 10 15 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007
INCHES* NOM 18 .100 .155 .130
MAX
MIN
MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10
MAX
4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15
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PIC16F87/88
18-Lead Plastic Small Outline (SO) - Wide, 300 mil (SOIC)
E p E1
D
2 B n 1
h
45
c A A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D h L c B
MIN
.093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0
INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12
MAX
MIN
.104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15
MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12
MAX
2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051
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PIC16F87/88
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E E1 p
D
B n
2 1
c A
A2
L A1
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic
Units Dimension Limits n p A A2 A1 E E1 D L c B
MIN
.068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0
INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5
MAX
MIN
.078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10
MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5
MAX
1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10
Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072
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PIC16F87/88
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN)
E E1 EXPOSED METAL PADS
Q D1 2 1 n R CH X 45 E2 L B D D2 p
TOP VIEW
BOTTOM VIEW
A2 A1 A3
A
Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top
Units Dimension Limits n p A A2 A1 A3 E E1 E2 D D1 D2 B L R Q CH
MIN
.000
.140
.140 .009 .020 .005 .012 .009
INCHES NOM 28 .026 BSC .033 .026 .0004 .008 REF .236 BSC .226 BSC .146 .236 BSC .226 BSC .146 .011 .024 .007 .016 .017
MAX
MIN
.039 .031 .002
.152
.152 .014 .030 .010 .026 .024 12
MILLIMETERS* NOM 28 0.65 BSC 0.85 0.65 0.00 0.01 0.20 REF 6.00 BSC 5.75 BSC 3.55 3.70 6.00 BSC 5.75 BSC 3.55 3.70 0.23 0.28 0.50 0.60 0.13 0.17 0.30 0.40 0.24 0.42
MAX
1.00 0.80 0.05
3.85
3.85 0.35 0.75 0.23 0.65 0.60 12
*Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC equivalent: mMO-220
Drawing No. C04-114
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NOTES:
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APPENDIX A: REVISION HISTORY APPENDIX B:
Revision A (November 2003)
Original data sheet for PIC16F87/88 devices.
DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
Revision B (August 2003)
The specifications in Section 18.0 "Electrical Characteristics" have been updated to include the addition of maximum specifications to the DC Characteristics tables, text clarification has been made to Section 4.6.2 "Clock Switching", and there have been minor updates to the data sheet text.
TABLE B-1:
Features Analog-to-Digital Converter
DIFFERENCES BETWEEN THE PIC16F87 AND PIC16F88
PIC16F87 N/A PIC16F88 10-bit, 7-channel
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NOTES:
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INDEX
A
A/D Acquisition Requirements ........................................ 117 ADIF Bit .................................................................... 116 Analog-to-Digital Converter ...................................... 113 Associated Registers ............................................... 120 Calculating Acquisition Time .................................... 117 Configuring Analog Port Pins ................................... 118 Configuring the Interrupt .......................................... 116 Configuring the Module ............................................ 116 Conversion Clock ..................................................... 118 Conversions ............................................................. 119 Converter Characteristics ........................................ 188 Delays ...................................................................... 117 Effects of a RESET .................................................. 120 GO/DONE Bit ........................................................... 116 Internal Sampling Switch (Rss) Impedance ............. 117 Operation During SLEEP ......................................... 120 Result Registers ....................................................... 119 Source Impedance ................................................... 117 Time Delays ............................................................. 117 Using the CCP Trigger ............................................. 120 Absolute Maximum Ratings ............................................. 163 ACK .................................................................................... 93 ADCON0 Register ...................................................... 14, 113 ADCON1 Register ...................................................... 15, 113 Addressable Universal Synchronous Asynchronous Receiver Transmitter. See USART. ADRESH Register ...................................................... 14, 113 ADRESH, ADRESL Register Pair .................................... 116 ADRESL Register ...................................................... 15, 113 ANSEL Register ..............................................15, 52, 58, 113 Application Notes AN556 (Implementing a Table Read) ........................ 25 AN578 (Use of the SSP Module in the I2C Multi-Master Environment) ........................... 87 AN607 (Power-up Trouble Shooting) ....................... 133 Assembler MPASM Assembler .................................................. 157 Asynchronous Reception Associated Registers ....................................... 105, 107 Asynchronous Transmission Associated Registers ............................................... 103 PWM .......................................................................... 84 RA0/AN0:RA1/AN1 Pins ............................................ 52 RA2/AN2/CVREF/VREF- Pin ....................................... 53 RA3/AN3/VREF+/C1OUT Pin ..................................... 53 RA4/T0CKI/C2OUT Pin ............................................. 54 RA5/MCLR/VPP Pin ................................................... 54 RA6/OSC2/CLKO Pin ................................................ 55 RA7/OSC1/CLKI Pin .................................................. 56 RB0 Pin ..................................................................... 59 RB1 Pin ..................................................................... 60 RB2 Pin ..................................................................... 61 RB3 Pin ..................................................................... 62 RB4 Pin ..................................................................... 63 RB5 Pin ..................................................................... 64 RB6 Pin ..................................................................... 65 RB7 Pin ..................................................................... 66 Recommended MCLR Circuit .................................. 133 SSP in I2C Mode ........................................................ 92 SSP in SPI Mode ....................................................... 90 System Clock ............................................................. 41 Timer0/WDT Prescaler .............................................. 67 Timer1 ....................................................................... 73 Timer2 ....................................................................... 79 USART Receive ................................................104, 106 USART Transmit ...................................................... 102 Watchdog Timer (WDT) ........................................... 141 BOR. See Brown-out Reset. BRGH bit ............................................................................ 99 Brown-out Reset (BOR) ............................ 129, 132, 133, 135 BOR Status (BOR Bit) ............................................... 24
C
C Compilers MPLAB C17 ............................................................. 158 MPLAB C18 ............................................................. 158 MPLAB C30 ............................................................. 158 Capture/Compare/PWM (CCP) ......................................... 81 Capture Mode ............................................................ 82 Capture, Compare and Timer1 Associated Registers ......................................... 83 CCP Pin Configuration ............................................... 83 CCP Prescaler ........................................................... 82 CCP Timer Resources ............................................... 81 CCP1IF ...................................................................... 82 CCPR1 ...................................................................... 82 CCPR1H:CCPR1L ..................................................... 82 Compare Mode .......................................................... 83 Special Event Trigger ........................................ 83 Special Trigger Output of CCP1 ........................ 83 PWM and Timer2 Associated Registers .................... 85 PWM Mode ................................................................ 84 PWM, Example Frequencies/Resolutions ................. 85 Software Interrupt Mode ............................................ 83 Timer1 Mode Selection .............................................. 83 CCP1CON Register ........................................................... 14 CCP1M0 Bit ....................................................................... 81 CCP1M1 Bit ....................................................................... 81 CCP1M2 Bit ....................................................................... 81 CCP1M3 Bit ....................................................................... 81 CCP1X Bit .......................................................................... 81 CCP1Y Bit .......................................................................... 81 CCPR1H Register .........................................................14, 81
B
Baud Rate Generator Associated Registers ................................................. 99 BF Bit ................................................................................. 92 Block Diagrams A/D ........................................................................... 116 Analog Input Model .......................................... 117, 125 Capture Mode Operation ........................................... 82 Comparator I/O Operating Modes ............................ 122 Comparator Output .................................................. 124 Comparator Voltage Reference ............................... 128 Compare Mode Operation ......................................... 83 Fail-Safe Clock Monitor ............................................ 144 In-Circuit Serial Programming Connection ............... 147 Interrupt Logic .......................................................... 139 On-Chip Reset Circuit .............................................. 132 PIC16F87 ..................................................................... 6 PIC16F88 ..................................................................... 7
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CCPR1L Register ......................................................... 14, 81 Clock Sources .................................................................... 39 Selection Using OSCCON Register ........................... 39 Clock Switching .................................................................. 39 Transition and the Watchdog Timer ........................... 40 CMCON Register ............................................................... 15 Code Examples Call of a Subroutine in Page 1 from Page 0 ............... 25 Changing Between Capture Prescalers ..................... 82 Changing Prescaler Assignment from WDT to Timer0 ................................................... 69 Erasing a FLASH Program Memory Row .................. 31 Implementing a Real-Time Clock Using a Timer1 Interrupt Service .................................... 77 Indirect Addressing .................................................... 26 Initializing PORTA ...................................................... 51 Reading a 16-bit Free-Running Timer ........................ 74 Reading Data EEPROM ............................................. 29 Reading FLASH Program Memory ............................ 30 Saving STATUS, W and PCLATH Registers ........... 140 Writing a 16-bit Free-Running Timer .......................... 74 Writing to Data EEPROM ........................................... 29 Writing to FLASH Program Memory ........................... 33 Code Protection ....................................................... 129, 147 Comparator Module ......................................................... 121 Analog Input Connection Considerations ................. 125 Associated Registers ............................................... 126 Configuration ............................................................ 122 Effects of a RESET .................................................. 125 Interrupts .................................................................. 124 Operation ................................................................. 123 Operation During SLEEP ......................................... 125 Outputs ..................................................................... 123 Reference ................................................................. 123 Response Time ........................................................ 123 Comparator Specifications ............................................... 175 Comparator Voltage Reference ....................................... 127 Associated Registers ............................................... 128 Computed GOTO ............................................................... 25 Configuration Bits ............................................................. 129 Crystal and Ceramic Resonators ....................................... 35 CVRCON Register ............................................................. 15 Demonstration Boards PICDEM 1 ................................................................ 160 PICDEM 17 .............................................................. 160 PICDEM 18R PIC18C601/801 ................................. 161 PICDEM 2 Plus ........................................................ 160 PICDEM 3 PIC16C92X ............................................ 160 PICDEM 4 ................................................................ 160 PICDEM LIN PIC16C43X ........................................ 161 PICDEM USB PIC16C7X5 ...................................... 161 PICDEM.net Internet/Ethernet ................................. 160 Development Support ...................................................... 157 Device Differences ........................................................... 199 Device Overview .................................................................. 5 Direct Addressing ............................................................... 26
E
EEADR Register ...........................................................16, 27 EEADRH Register .........................................................16, 27 EECON1 Register .........................................................16, 27 EECON2 Register .........................................................16, 27 EEDATA Register .........................................................16, 27 EEDATH Register .........................................................16, 27 Electrical Characteristics .................................................. 163 Endurance ........................................................................... 1 Errata ................................................................................... 4 Evaluation and Programming Tools ................................. 161 Exiting SLEEP with an Interrupt ......................................... 50 External Clock Input ........................................................... 36 External Clock Input (RA4/T0CKI). See Timer0. External Interrupt Input (RB0/INT). See Interrupt Sources. External Reference Signal ............................................... 123
F
Fail-Safe Clock Monitor .............................................129, 144 FLASH Program Memory ................................................... 27 Associated Registers ................................................. 34 EEADR Register ........................................................ 27 EEADRH Register ..................................................... 27 EECON1 Register ...................................................... 27 EECON2 Register ...................................................... 27 EEDATA Register ...................................................... 27 EEDATH Register ...................................................... 27 Erasing ....................................................................... 30 Reading ..................................................................... 30 Writing ........................................................................ 32 FSR Register ..........................................................14, 15, 26
D
Data EEPROM Memory ..................................................... 27 Associated Registers ................................................. 34 EEADR Register ........................................................ 27 EEADRH Register ...................................................... 27 EECON1 Register ...................................................... 27 EECON2 Register ...................................................... 27 EEDATA Register ...................................................... 27 EEDATH Register ...................................................... 27 Operation During Code Protect .................................. 34 Protection Against Spurious Writes ............................ 34 Reading ...................................................................... 29 Write Complete Flag (EEIF Bit) .................................. 27 Writing ........................................................................ 29 Data Memory Special Function Registers ........................................ 14 DC and AC Characteristics Graphs and Tables ................................................... 191 DC Characteristics Internal RC Accuracy ............................................... 172 PIC16F87/88, PIC16LF87/88 ................................... 173 Power-down and Supply Current ............................. 166 Supply Voltage ......................................................... 165
I
I/O Ports ............................................................................. 51 PORTA ...................................................................... 51 PORTB ...................................................................... 57 TRISB Register .......................................................... 57 I2C Addressing ................................................................. 93 Associated Registers ................................................. 95 Master Mode .............................................................. 95 Mode .......................................................................... 92 Mode Selection .......................................................... 92 Multi-Master Mode ..................................................... 95 Reception ................................................................... 93 SCL and SDA pins ..................................................... 92 Slave Mode ................................................................ 92 Transmission ............................................................. 93 ID Locations ..............................................................129, 147 In-Circuit Debugger .......................................................... 147 In-Circuit Serial Programming .......................................... 129
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In-Circuit Serial Programming (ICSP) .............................. 147 INDF Register .........................................................14, 15, 26 Indirect Addressing ............................................................ 26 Instruction Set .................................................................. 149 ADDLW .................................................................... 151 ADDWF .................................................................... 151 ANDLW .................................................................... 151 ANDWF .................................................................... 151 BCF .......................................................................... 151 BSF .......................................................................... 151 BTFSC ..................................................................... 152 BTFSS ..................................................................... 152 CALL ........................................................................ 152 CLRF ........................................................................ 152 CLRW ...................................................................... 152 CLRWDT .................................................................. 152 COMF ...................................................................... 153 DECF ....................................................................... 153 DECFSZ ................................................................... 153 Descriptions ............................................................. 151 Format ...................................................................... 149 GOTO ...................................................................... 153 INCF ......................................................................... 153 INCFSZ .................................................................... 153 IORLW ..................................................................... 154 IORWF ..................................................................... 154 MOVF ....................................................................... 154 MOVLW ................................................................... 154 MOVWF ................................................................... 154 NOP ......................................................................... 154 Read-Modify-Write Operations ................................ 149 RETFIE .................................................................... 155 RETLW .................................................................... 155 RETURN .................................................................. 155 RLF .......................................................................... 155 RRF .......................................................................... 155 SLEEP ..................................................................... 155 SUBLW .................................................................... 156 SUBWF .................................................................... 156 Summary Table ........................................................ 150 SWAPF .................................................................... 156 XORLW .................................................................... 156 XORWF .................................................................... 156 INT Interrupt (RB0/INT). See Interrupt Sources. INTCON Register GIE Bit ........................................................................ 19 INTE Bit ...................................................................... 19 INTF Bit ...................................................................... 19 PEIE Bit ...................................................................... 19 RBIE Bit ..................................................................... 19 RBIF Bit ...................................................................... 19 TMR0IE Bit ................................................................. 19 Internal Oscillator Block ..................................................... 37 INTRC Modes ............................................................ 38 Internal Reference Signal ................................................. 123 Interrupt Sources ...................................................... 129, 138 RB0/INT Pin, External .............................................. 140 TMR0 Overflow ........................................................ 140 USART Receive/Transmit Complete ......................... 97 Interrupts RB7:RB4 Port Change ............................................... 57 Interrupts, Context Saving During .................................... 140 Interrupts, Enable Bits A/D Converter Interrupt Enable (ADIE Bit) ................ 20 CCP1 Interrupt Enable (CCP1IE Bit) ......................... 20 Comparator Interrupt Enable (CMIE Bit) .................... 22 EEPROM Write Operation Interrupt Enable (EEIE Bit) ........................................................... 22 Global Interrupt Enable (GIE Bit) ........................19, 138 Interrupt-on-Change (RB7:RB4) Enable (RBIE Bit) ......................................................... 140 Oscillator Fail Interrupt Enable (OSFIE Bit) ............... 22 Peripheral Interrupt Enable (PEIE Bit) ....................... 19 Port Change Interrupt Enable (RBIE Bit) ................... 19 RB0/INT Enable (INTE Bit) ........................................ 19 Synchronous Serial Port (SSP) Interrupt Enable (SSPIE Bit) ........................................................ 20 TMR0 Overflow Enable (TMR0IE Bit) ........................ 19 TMR1 Overflow Interrupt Enable (TMR1IE Bit) ......... 20 TMR2 to PR2 Match Interrupt Enable (TMR2IE Bit) ...................................................... 20 USART Interrupt Enable (RCIE Bit) ........................... 20 USART Transmit Interrupt Enable (TXIE Bit) ............ 20 Interrupts, Flag Bits A/D Converter Interrupt Flag (ADIF Bit) ..................... 21 CCP1 Interrupt Flag (CCP1IF Bit) ............................. 21 Comparator Interrupt Flag (CMIF Bit) ........................ 23 EEPROM Write Operation Interrupt Flag (EEIF Bit) ........................................................... 23 Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ....................................................19, 140 Oscillator Fail Interrupt Flag (OSFIF Bit) ................... 23 RB0/INT Flag (INTF Bit) ............................................ 19 Synchronous Serial Port (SSP) Interrupt Flag (SSPIF Bit) ......................................................... 21 TMR0 Overflow Flag (TMR0IF Bit) .......................... 140 TMR1 Overflow Interrupt Flag (TMR1IF Bit) .............. 21 TMR2 to PR2 Interrupt Flag (TMR2IF Bit) ................. 21 USART Receive Interrupt Flag (RCIF Bit) ................. 21 USART Transmit Interrupt Flag (TXIF Bit) ................. 21 INTRC Modes Adjustment ................................................................. 38
L
Loading of PC .................................................................... 25 Low-Voltage ICSP Programming ..................................... 148
M
Master Clear (MCLR) MCLR Reset, Normal Operation .......................132, 135 MCLR Reset, SLEEP ........................................132, 135 Operation and ESD Protection ................................ 133 Memory Organization ........................................................ 11 Data Memory ............................................................. 11 Program Memory ....................................................... 11 MPLAB ASM30 Assembler, Linker, Librarian .................. 158 MPLAB ICD 2 In-Circuit Debugger .................................. 159 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator ................................................... 159 MPLAB ICE 4000 High Performance Universal In-Circuit Emulator ................................................... 159 MPLAB Integrated Development Environment Software ............................................. 157 MPLINK Object Linker/MPLIB Object Librarian ............... 158
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O
Opcode Field Descriptions ............................................... 149 OPTION Register INTEDG Bit ................................................................ 18 PS2:PS0 Bits .............................................................. 18 PSA Bit ....................................................................... 18 RBPU Bit .................................................................... 18 T0CS Bit ..................................................................... 18 T0SE Bit ..................................................................... 18 OSCCON Register ............................................................. 15 Oscillator Configuration ...................................................... 35 ECIO .......................................................................... 35 EXTRC ..................................................................... 134 HS ...................................................................... 35, 134 INTIO1 ........................................................................ 35 INTIO2 ........................................................................ 35 INTRC ...................................................................... 134 LP ....................................................................... 35, 134 RC ........................................................................ 35, 37 RCIO .......................................................................... 35 XT ....................................................................... 35, 134 Oscillator Control Register Modifying IRCF Bits ................................................... 41 Clock Transition Sequence ................................ 41 Oscillator Delay upon Power-up, Wake-up and Clock Switching .......................................................... 42 Oscillator Start-up Timer (OST) ............................... 129, 133 Oscillator Switching ............................................................ 39 OSCTUNE Register ........................................................... 15 PIR2 Register .................................................................... 14 CMIF Bit ..................................................................... 23 EEIF Bit ...................................................................... 23 OSFIF Bit ................................................................... 23 POP ................................................................................... 25 POR. See Power-on Reset. PORTA ................................................................................ 8 Associated Register Summary .................................. 52 PORTA Register ........................................................ 14 PORTB ................................................................................ 9 Associated Register Summary .................................. 58 PORTB Register ........................................................ 14 Pull-up Enable (RBPU Bit) ......................................... 18 RB0/INT Edge Select (INTEDG Bit) .......................... 18 RB0/INT Pin, External .............................................. 140 RB2/SDO/RX/DT Pin ............................................98, 99 RB5/SS/TX/CK Pin .................................................... 98 RB7:RB4 Interrupt-on-Change ................................ 140 RB7:RB4 Interrupt-on-Change Enable (RBIE Bit) ......................................................... 140 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ....................................................19, 140 TRISB Register .....................................................16, 97 PORTB Register ................................................................ 16 Postscaler, WDT Assignment (PSA Bit) ................................................ 18 Rate Select (PS2:PS0 Bits) ....................................... 18 Power Managed Modes ..................................................... 43 RC_RUN .................................................................... 43 SEC_RUN .................................................................. 44 SEC_RUN/RC_RUN to Primary Clock Source .......... 45 Power-down Mode. See SLEEP. Power-on Reset (POR) ............................. 129, 132, 133, 135 POR Status (POR Bit) ............................................... 24 Power Control (PCON) Register .............................. 134 Power-down (PD Bit) ............................................... 132 Time-out (TO Bit) ................................................17, 132 Power-up Timer (PWRT) ..........................................129, 133 PR2 Register ................................................................15, 79 Prescaler, Timer0 Assignment (PSA Bit) ................................................ 18 Rate Select (PS2:PS0 Bits) ....................................... 18 PRO MATE II Universal Device Programmer .................. 159 Program Counter RESET Conditions ................................................... 135 Program Memory Interrupt Vector .......................................................... 11 Map and Stack PIC16F87/88 ..................................................... 11 Paging ........................................................................ 25 RESET Vector ........................................................... 11 Program Verification ........................................................ 147 PUSH ................................................................................. 25
P
Packaging Information ..................................................... 193 Marking .................................................................... 193 Paging, Program Memory .................................................. 25 PCL Register .......................................................... 14, 15, 25 PCLATH Register ................................................... 14, 15, 25 PCON Register .......................................................... 15, 134 BOR Bit ...................................................................... 24 POR Bit ...................................................................... 24 PICkit 1 FLASH Starter Kit ............................................... 161 PICSTART Plus Development Programmer .................... 159 PIE1 Register ..................................................................... 15 ADIE Bit ...................................................................... 20 CCP1IE Bit ................................................................. 20 RCIE Bit ..................................................................... 20 SSPIE Bit ................................................................... 20 TMR1IE Bit ................................................................. 20 TMR2IE Bit ................................................................. 20 TXIE Bit ...................................................................... 20 PIE2 Register ..................................................................... 15 CMIE Bit ..................................................................... 22 EEIE Bit ...................................................................... 22 OSFIE Bit ................................................................... 22 Pinout Descriptions PIC16F87/88 ................................................................ 8 PIR1 Register ..................................................................... 14 ADIF Bit ...................................................................... 21 CCP1IF Bit ................................................................. 21 RCIF Bit ...................................................................... 21 SSPIF Bit .................................................................... 21 TMR1IF Bit ................................................................. 21 TMR2IF Bit ................................................................. 21 TXIF Bit ...................................................................... 21
R
R/W Bit ............................................................................... 93 RA0/AN0 Pin ........................................................................ 8 RA1/AN1 Pin ........................................................................ 8 RA2/AN2/CVREF/VREF- Pin .................................................. 8 RA3/AN3/VREF+/C1OUT Pin ............................................... 8 RA4/AN4/T0CKI/C2OUT Pin ............................................... 8 RA5/MCLR/VPP Pin ............................................................. 8 RA6/OSC2/CLKO Pin .......................................................... 8 RA7/OSC1/CLKI Pin ............................................................ 8
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RB0/INT/CCP1 Pin ............................................................... 9 RB1/SDI/SDA Pin ................................................................. 9 RB2/SDO/RX/DT Pin ........................................................... 9 RB3/PGM/CCP1 Pin ............................................................ 9 RB4/SCK/SCL Pin ................................................................ 9 RB5/SS/TX/CK Pin ............................................................... 9 RB6/AN5/PGC/T1OSO/T1CKI Pin ....................................... 9 RB7/AN6/PGD/T1OSI Pin .................................................... 9 RBIF Bit .............................................................................. 57 RCIO Oscillator .................................................................. 37 RCREG Register ................................................................ 14 RCSTA Register ................................................................. 14 ADDEN Bit ................................................................. 98 CREN Bit .................................................................... 98 FERR Bit .................................................................... 98 RX9 Bit ....................................................................... 98 RX9D Bit .................................................................... 98 SPEN Bit .............................................................. 97, 98 SREN Bit .................................................................... 98 Receive Overflow Indicator Bit, SSPOV ............................. 89 Register File ....................................................................... 12 Register File Map PIC16F87 ................................................................... 12 PIC16F88 ................................................................... 13 Registers ADCON0 (A/D Control 0) ......................................... 114 ADCON1 (A/D Control 1) ......................................... 115 ANSEL (Analog Select) ............................................ 113 CCP1CON (Capture/Compare/PWM Control 1) ........................................................... 81 CMCON (Comparator Control) ................................ 121 CONFIG1 (Configuration Word 1) ............................ 130 CONFIG2 (Configuration Word 2) ............................ 131 CVRCON (Comparator Voltage Reference Control) ........................................... 127 EECON1 (Data EEPROM Access Control 1) ........................................................... 28 FSR ............................................................................ 26 Initialization Conditions (table) ......................... 135-136 INTCON (Interrupt Control) ........................................ 19 OPTION ..................................................................... 18 OPTION_REG ........................................................... 68 OSCCON (Oscillator Control) .................................... 40 OSCTUNE (Oscillator Tuning) ................................... 38 PCON (Power Control) .............................................. 24 PIE1 (Peripheral Interrupt Enable 1) .......................... 20 PIE2 (Peripheral Interrupt Enable 2) .......................... 22 PIR1 (Peripheral Interrupt Status 1) ........................... 21 PIR2 (Peripheral Interrupt Status 2) ........................... 23 RCSTA (Receive Status and Control) ........................ 98 Special Function, Summary ....................................... 14 SSPCON (Synchronous Serial Port Control) ............................................ 89 SSPSTAT (Synchronous Serial Port Status) .............................................. 88 STATUS ..................................................................... 17 T1CON (Timer1 Control) ............................................ 72 T2CON (Timer2 Control) ............................................ 80 TXSTA (Transmit Status and Control) ....................... 97 WDTCON (Watchdog Timer Control) ....................... 142 RESET ......................................................................129, 132 Brown-out Reset (BOR). See Brown-out Reset (BOR). MCLR RESET. See MCLR. Power-on Reset (POR). See Power-on Reset (POR). RESET Conditions for All Registers ........................ 135 RESET Conditions for PCON Register .................... 135 RESET Conditions for Program Counter ................. 135 RESET Conditions for STATUS Register ................ 135 WDT Reset. See Watchdog Timer (WDT). Revision History ............................................................... 199 RP0 Bit ............................................................................... 11 RP1 Bit ............................................................................... 11
S
SCI. See USART. SCL .................................................................................... 92 Serial Communication Interface. See USART. Slave Mode SCL ............................................................................ 92 SDA ........................................................................... 92 SLEEP .............................................................. 129, 132, 145 Software Simulator (MPLAB SIM) ................................... 158 Software Simulator (MPLAB SIM30) ............................... 158 SPBRG Register ................................................................ 15 Special Event Trigger ...................................................... 120 Special Features of the CPU ........................................... 129 Special Function Registers ................................................ 14 Special Function Registers (SFRs) .................................... 14 SPI Associated Registers ................................................. 90 Serial Clock ................................................................ 87 Serial Data In ............................................................. 87 Serial Data Out .......................................................... 87 Slave Select ............................................................... 87 SSP ACK ........................................................................... 92 I2C I2C Operation ..................................................... 92 SSPADD Register .............................................................. 15 SSPBUF Register .............................................................. 14 SSPCON Register ............................................................. 14 SSPOV .............................................................................. 89 SSPOV Bit ......................................................................... 92 SSPSTAT Register ............................................................ 15 Stack .................................................................................. 25 Overflows ................................................................... 25 Underflow .................................................................. 25 STATUS Register C Bit ........................................................................... 17 DC Bit ........................................................................ 17 IRP Bit ....................................................................... 17 PD Bit .................................................................17, 132 RP Bit ........................................................................ 17 TO Bit .................................................................17, 132 Z Bit ........................................................................... 17 Synchronous Master Reception Associated Registers ............................................... 110 Synchronous Master Transmission Associated Registers ............................................... 109 Synchronous Serial Port (SSP) ......................................... 87 Overview .................................................................... 87 SPI Mode ................................................................... 87 Synchronous Slave Reception Associated Registers ............................................... 112 Synchronous Slave Transmission Associated Registers ............................................... 111
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P
IC
16F
8 7 /8 8
T
T1CKPS0 Bit ...................................................................... 72 T1CKPS1 Bit ...................................................................... 72 T1CON Register ................................................................. 14 T1OSCEN Bit ..................................................................... 72 T1SYNC Bit ........................................................................ 72 T2CKPS0 Bit ...................................................................... 80 T2CKPS1 Bit ...................................................................... 80 T2CON Register ................................................................. 14 TAD ................................................................................... 118 Time-out Sequence .......................................................... 134 Timer0 ................................................................................ 67 Associated Registers ................................................. 69 Clock Source Edge Select (T0SE Bit) ........................ 18 Clock Source Select (T0CS Bit) ................................. 18 External Clock ............................................................ 68 Interrupt ...................................................................... 67 Operation ................................................................... 67 Overflow Enable (TMR0IE Bit) ................................... 19 Overflow Flag (TMR0IF Bit) ..................................... 140 Overflow Interrupt ..................................................... 140 Prescaler .................................................................... 68 T0CKI ......................................................................... 68 Timer1 ................................................................................ 71 Associated Registers ................................................. 77 Asynchronous Counter Mode ..................................... 74 Reading and Writing .......................................... 74 Capacitor Selection .................................................... 75 Counter Operation ...................................................... 73 Operation ................................................................... 71 Operation in Timer Mode ........................................... 73 Oscillator .................................................................... 75 Oscillator Layout Considerations ............................... 75 Prescaler .................................................................... 76 Resetting Timer1 Register Pair .................................. 76 Resetting Timer1 Using a CCP Trigger Output .......... 75 Synchronized Counter Mode ...................................... 73 Use as a Real-Time Clock ......................................... 76 Timer2 ................................................................................ 79 Associated Registers ................................................. 80 Output ........................................................................ 79 Postscaler .................................................................. 79 Prescaler .................................................................... 79 Prescaler and Postscaler ........................................... 79 Timing Diagrams A/D Conversion ........................................................ 189 Asynchronous Master Transmission ........................ 103 Asynchronous Master Transmission (Back to Back) .................................................. 103 Asynchronous Reception ......................................... 104 Asynchronous Reception with Address Byte First ............................................ 107 Asynchronous Reception with Address Detect ........ 107 Brown-out Reset ...................................................... 179 Capture/Compare/PWM (CCP1) .............................. 181 CLKO and I/O ........................................................... 178 External Clock .......................................................... 177 Fail-Safe Clock Monitor ............................................ 144 I2C Bus Data ............................................................ 185 I2C Bus START/STOP Bits ...................................... 184 I2C Reception (7-bit Address) .................................... 94 I2C Transmission (7-bit Address) ............................... 94 Primary System Clock after RESET (EC, RC, INTRC) ............................................... 48
Primary System Clock after RESET (HS, XT, LP) ..... 47 PWM Output .............................................................. 84 RESET, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer .............................. 179 Slow Rise Time (MCLR Tied to VDD Through RC Network) ...................................... 138 SPI Master Mode ....................................................... 91 SPI Master Mode (CKE = 0, SMP = 0) .................... 182 SPI Master Mode (CKE = 1, SMP = 1) .................... 182 SPI Slave Mode (CKE = 0) .................................91, 183 SPI Slave Mode (CKE = 1) .................................91, 183 Switching to SEC_RUN Mode ................................... 44 Synchronous Reception (Master Mode, SREN) ...... 111 Synchronous Transmission ..................................... 109 Synchronous Transmission (Through TXEN) .......... 109 Time-out Sequence on Power-up (MCLR Tied to VDD Through Pull-up Resistor) .................... 137 Time-out Sequence on Power-up (MCLR Tied to VDD Through RC Network): Case 1 ............. 137 Time-out Sequence on Power-up (MCLR Tied to VDD Through RC Network): Case 2 ............. 137 Timer0 and Timer1 External Clock .......................... 180 Timer1 Incrementing Edge ........................................ 73 Transition Between SEC_RUN/RC_RUN and Primary Clock ............................................. 46 Two-Speed Start-up Mode ....................................... 143 USART Synchronous Receive (Master/Slave) ........ 187 USART Synchronous Transmission (Master/Slave) ................................................. 187 Wake-up from SLEEP via Interrupt .......................... 146 XT, HS, LP, EC and EXTRC to RC_RUN Mode ........ 43 Timing Parameter Symbology .......................................... 176 Timing Requirements A/D Conversion ........................................................ 189 Capture/Compare/PWM (CCP1) ............................. 181 CLKO and I/O .......................................................... 178 External Clock .......................................................... 177 I2C Bus Data ............................................................ 186 I2C Bus START/STOP Bits ...................................... 185 RESET, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset .............................................. 179 SPI Mode ................................................................. 184 Timer0 and Timer1 External Clock .......................... 180 USART Synchronous Receive ................................. 187 USART Synchronous Transmission ........................ 187 TMR0 Register ................................................................... 14 TMR1CS Bit ....................................................................... 72 TMR1H Register ................................................................ 14 TMR1L Register ................................................................. 14 TMR1ON Bit ....................................................................... 72 TMR2 Register ................................................................... 14 TMR2ON Bit ....................................................................... 80 TMRO Register .................................................................. 16 TOUTPS0 Bit ..................................................................... 80 TOUTPS1 Bit ..................................................................... 80 TOUTPS2 Bit ..................................................................... 80 TOUTPS3 Bit ..................................................................... 80 TRISA Register .............................................................15, 51 TRISB Register .................................................................. 15 Two-Speed Clock Start-up Mode ..................................... 143 Two-Speed Start-up ......................................................... 129 TXREG Register ................................................................ 14
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TXSTA Register ................................................................. 15 BRGH Bit ................................................................... 97 CSRC Bit .................................................................... 97 SYNC Bit .................................................................... 97 TRMT Bit .................................................................... 97 TX9 Bit ....................................................................... 97 TX9D Bit ..................................................................... 97 TXEN Bit .................................................................... 97
V
VDD Pin ................................................................................ 9 Voltage Reference Specifications .................................... 175 VSS Pin ................................................................................ 9
W
Wake-up from SLEEP ...............................................129, 146 Interrupts ................................................................. 135 MCLR Reset ............................................................ 135 WDT Reset .............................................................. 135 Wake-up Using Interrupts ................................................ 146 Watchdog Timer (WDT) ............................................129, 141 Associated Registers ............................................... 142 WDT Reset, Normal Operation .........................132, 135 WDT Reset, SLEEP ..........................................132, 135 WCOL ................................................................................ 89 WDTCON Register ............................................................ 16 Write Collision Detect Bit, WCOL ...................................... 89 WWW, On-Line Support ...................................................... 4
U
USART ............................................................................... 97 Address Detect Enable (ADDEN Bit) ......................... 98 Asynchronous Mode ................................................ 102 Asynchronous Receive (9-bit Mode) ........................ 106 Asynchronous Receive with Address Detect. See Asynchronous Receive (9-bit Mode). Asynchronous Receiver ........................................... 104 Asynchronous Reception ......................................... 105 Asynchronous Transmitter ....................................... 102 Baud Rate Generator (BRG) ...................................... 99 Baud Rate Formula ............................................ 99 Baud Rates, Asynchronous Mode (BRGH = 0) .............................................. 100 Baud Rates, Asynchronous Mode (BRGH = 1) .............................................. 100 High Baud Rate Select (BRGH Bit) .................... 97 INTRC Baud Rates, Asynchronous Mode (BRGH = 0) .............................................. 101 INTRC Baud Rates, Asynchronous Mode (BRGH = 1) .............................................. 101 INTRC Operation ............................................... 99 Low-power Mode Operation ............................... 99 Sampling ............................................................ 99 Clock Source Select (CSRC Bit) ................................ 97 Continuous Receive Enable (CREN Bit) .................... 98 Framing Error (FERR Bit) .......................................... 98 Mode Select (SYNC Bit) ............................................ 97 Receive Data, 9th bit (RX9D Bit) ............................... 98 Receive Enable, 9-bit (RX9 Bit) ................................. 98 Serial Port Enable (SPEN Bit) .............................. 97, 98 Single Receive Enable (SREN Bit) ............................ 98 Synchronous Master Mode ...................................... 108 Synchronous Master Reception ............................... 110 Synchronous Master Transmission .......................... 108 Synchronous Slave Mode ........................................ 111 Synchronous Slave Reception ................................. 112 Synchronous Slave Transmit ................................... 111 Transmit Data, 9th Bit (TX9D) .................................... 97 Transmit Enable (TXEN Bit) ....................................... 97 Transmit Enable, Nine-bit (TX9 Bit) ........................... 97 Transmit Shift Register Status (TRMT Bit) ................. 97 USART Synchronous Receive Requirements .................. 187
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PIC16F87/88
NOTES:
DS30487B-page 208
2003 Microchip Technology Inc.
PIC16F87/88
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape(R) or Microsoft(R) Internet Explorer. Files are also available for FTP download from our FTP site.
SYSTEMS INFORMATION AND UPGRADE HOT LINE
The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive the most current upgrade kits. The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 042003
Connecting to the Microchip Internet Web Site
The Microchip web site is available at the following URL: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events
2003 Microchip Technology Inc.
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DS30487B-page 209
PIC16F87/88
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC16F87/88 Questions: 1. What are the best features of this document? Y N Literature Number: DS30487B FAX: (______) _________ - _________
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS30487B-page 210
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2003 Microchip Technology Inc.
PIC16F87/88
PIC16F87/88 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples:
a) b) Device PIC16F87: Standard VDD range PIC16F87T: (Tape and Reel) PIC16LF87: Extended VDD range PIC16F87-I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F87-I/SO = Industrial temp., SOIC package, normal VDD limits.
Temperature Range
I
= =
0C to +70C -40C to +85C
Package
P SO SS ML
= = = =
PDIP SOIC SSOP QFN Note 1: F = CMOS FLASH LF = Low-power CMOS FLASH T = in tape and reel - SOIC, SSOP packages only.
Pattern
QTP, SQTP, ROM Code (factory specified) or Special Requirements. Blank for OTP and Windowed devices.
2:
2003 Microchip Technology Inc.
Preliminary
DS30487B-page 211
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com
ASIA/PACIFIC
Australia
Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Korea
168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934
Singapore
200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850
China - Beijing
Unit 915 Bei Hai Wan Tai Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104
Atlanta
3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307
Taiwan
Kaohsiung Branch 30F - 1 No. 8 Min Chuan 2nd Road Kaohsiung 806, Taiwan Tel: 886-7-536-4818 Fax: 886-7-536-4803
Boston
2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821
China - Chengdu
Rm. 2401-2402, 24th Floor, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-86766200 Fax: 86-28-86766599
Taiwan
Taiwan Branch 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Chicago
333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075
China - Fuzhou
Unit 28F, World Trade Plaza No. 71 Wusi Road Fuzhou 350001, China Tel: 86-591-7503506 Fax: 86-591-7503521
Dallas
4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924
EUROPE
Austria
Durisolstrasse 2 A-4600 Wels Austria Tel: 43-7242-2244-399 Fax: 43-7242-2244-393
China - Hong Kong SAR
Unit 901-6, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431
Detroit
Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260
Denmark
Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45-4420-9895 Fax: 45-4420-9910
China - Shanghai
Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
Kokomo
2767 S. Albright Road Kokomo, IN 46902 Tel: 765-864-8360 Fax: 765-864-8387
France
Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Los Angeles
18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338
China - Shenzhen
Rm. 1812, 18/F, Building A, United Plaza No. 5022 Binhe Road, Futian District Shenzhen 518033, China Tel: 86-755-82901380 Fax: 86-755-8295-1393
Germany
Steinheilstrasse 10 D-85737 Ismaning, Germany Tel: 49-89-627-144-0 Fax: 49-89-627-144-44
Phoenix
2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-4338
China - Shunde
Room 401, Hongjian Building No. 2 Fengxiangnan Road, Ronggui Town Shunde City, Guangdong 528303, China Tel: 86-765-8395507 Fax: 86-765-8395571
Italy
Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781
San Jose
2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955
China - Qingdao
Rm. B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205
Netherlands
P. A. De Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340
Toronto
6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509
India
Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062
United Kingdom
505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820
07/28/03
Japan
Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122
DS30487B-page 212
Preliminary
2003 Microchip Technology Inc.

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